RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 05:01:59 +01:00
Code Issues Projects Releases Wiki Activity
202,140 Commits 4 Branches 5 Tags
Commit Graph

6 Commits

Author SHA1 Message Date
David Sherwood
1652ed61e6 [SVE][CodeGen] Add README for SVE-related warnings in tests 
I have added a new file:

  llvm/test/CodeGen/AArch64/README

that describes what to do in the event one of the SVE codegen tests
fails the warnings check. In addition, I've added comments to all
the relevant SVE tests pointing users at the README file.

Differential Revision: https://reviews.llvm.org/D83467
 2020-07-14 08:31:10 +01:00
David Sherwood
4ab4d5df20 [SVE] Add checks for no warnings in SVE tests 
There are now quite a few SVE tests in LLVM and Clang that do not
emit warnings related to invalid use of EVT::getVectorNumElements()
and VectorType::getNumElements(). For these tests I have added
additional checks that there are no warnings in order to prevent
any future regressions.

Differential Revision: https://reviews.llvm.org/D80712
 2020-06-18 13:18:01 +01:00
David Sherwood
009f73b707 Revert "[SVE] Add checks for no warnings in SVE tests" 
This reverts commit fb495c31701b2cd697cf4282f63764c9cefd49c0.

Was causing test failures and broke buildbot.
 2020-06-18 08:03:31 +01:00
David Sherwood
4399d793fa [SVE] Add checks for no warnings in SVE tests 
There are now quite a few SVE tests in LLVM and Clang that do not
emit warnings related to invalid use of EVT::getVectorNumElements()
and VectorType::getNumElements(). For these tests I have added
additional checks that there are no warnings in order to prevent
any future regressions.

Differential Revision: https://reviews.llvm.org/D80712
 2020-06-18 07:49:48 +01:00
Fangrui Song
1e7c397a16 [CodeGenPrepare] Make TargetPassConfig required 
The code paths in the absence of TargetMachine, TargetLowering or
TargetRegisterInfo are poorly tested. As rL285987 said, requiring
TargetPassConfig allows us to delete many (untested) checks littered
everywhere.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73754
 2020-02-02 09:28:45 -08:00
Sander de Smalen
c07e22a824 Add support for (expressing) vscale. 
In LLVM IR, vscale can be represented with an intrinsic. For some targets,
this is equivalent to the constexpr:

  getelementptr <vscale x 1 x i8>, <vscale x 1 x i8>* null, i32 1

This can be used to propagate the value in CodeGenPrepare.

In ISel we add a node that can be legalized to one or more
instructions to materialize the runtime vector length.

This patch also adds SVE CodeGen support for VSCALE, which maps this
node to RDVL instructions (for scaled multiples of 16bytes) or CNT[HSD]
instructions (scaled multiples of 2, 4, or 8 bytes, respectively).

Reviewers: rengolin, cameron.mcinally, hfinkel, sebpop, SjoerdMeijer, efriedma, lattner

Reviewed by: efriedma

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68203
 2020-01-22 10:09:27 +00:00