Evan Cheng
2a527c3419
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin
6ed9f9c9c5
Enhance tests to include shifted-register operand testing.
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llvm-svn: 74490
2009-06-30 01:02:20 +00:00
David Goodwin
4f53387d26
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
David Goodwin
e7df96eedf
Thumb-2 tests
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llvm-svn: 74464
2009-06-29 22:25:22 +00:00
David Goodwin
9e1280adf3
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Evan Cheng
093adf3ff9
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
David Goodwin
90fc344e41
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
David Goodwin
4997a459c7
Thumb-2 tests
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llvm-svn: 74345
2009-06-26 22:37:07 +00:00
David Goodwin
921faa64cd
Thumb-2 has CLZ.
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llvm-svn: 74322
2009-06-26 20:47:43 +00:00
David Goodwin
9da977f216
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
Daniel Dunbar
23337e07ce
More spelling Count as count.
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llvm-svn: 74306
2009-06-26 18:35:07 +00:00
Daniel Dunbar
fa37f8bf95
Spell Count as count.
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llvm-svn: 74298
2009-06-26 18:21:54 +00:00
David Goodwin
4a98908300
Add Thumb-2 tests.
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llvm-svn: 74295
2009-06-26 18:10:30 +00:00
David Goodwin
46eb5a7a2d
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
David Goodwin
b2c485c6bd
ORN and BIC tests.
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llvm-svn: 74289
2009-06-26 16:20:06 +00:00
David Goodwin
877790aa5f
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
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Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
Evan Cheng
7883ae3121
Fix tests: Count -> count.
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llvm-svn: 74282
2009-06-26 07:05:57 +00:00
Evan Cheng
da10be895c
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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llvm-svn: 74276
2009-06-26 05:59:16 +00:00
Daniel Dunbar
be7f3311ad
Fix spelling of 'count'
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llvm-svn: 74249
2009-06-26 01:33:02 +00:00
Evan Cheng
4ac765118d
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
David Goodwin
74414108e9
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
Evan Cheng
0cced3daa8
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
Evan Cheng
e8c58ee743
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
Evan Cheng
f7814163db
We should run these tests as well.
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llvm-svn: 74121
2009-06-24 21:36:26 +00:00
Evan Cheng
b4139189b0
Move thumb and thumb2 tests into separate directories.
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llvm-svn: 74068
2009-06-24 06:36:07 +00:00
