Nate Begeman
81c97654da
Clean up floating point instruction selection.
...
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter
llvm-svn: 15913
2004-08-19 05:20:54 +00:00
Chris Lattner
6ddb5d6c76
Convert all of the DForm_6* operations, which makes all of the Zimm16 users
...
dead.
llvm-svn: 15754
2004-08-15 05:46:14 +00:00
Chris Lattner
41839ea5cd
Convert the DForm_4 over to the asmprintergen
...
llvm-svn: 15751
2004-08-15 05:20:16 +00:00
Chris Lattner
e19e10e800
Print mflr using the asmwriter generator
...
llvm-svn: 15749
2004-08-14 23:27:29 +00:00
Nate Begeman
557f61c4d6
Add indexed forms of load doubleword and load word algebraic for 64 bit targets
...
llvm-svn: 15743
2004-08-14 22:12:20 +00:00
Nate Begeman
48359fbcd0
Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files
...
llvm-svn: 15710
2004-08-13 02:19:26 +00:00
Misha Brukman
0b67e02e9c
Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes
...
llvm-svn: 15668
2004-08-11 23:33:34 +00:00
Misha Brukman
08b8a09113
Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes
...
llvm-svn: 15667
2004-08-11 20:56:14 +00:00
Misha Brukman
7325a6c790
Add doubleword load/store (64-bit only).
...
llvm-svn: 15665
2004-08-11 15:54:36 +00:00
Nate Begeman
b74ee41754
Fix casts of float to unsigned long
...
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
llvm-svn: 15626
2004-08-10 20:42:36 +00:00
Misha Brukman
ba013330a8
Use instruction formats as defined in the PowerPC ISA manual
...
llvm-svn: 15577
2004-08-09 17:24:04 +00:00
Misha Brukman
07f8b33325
Remove unused opcodes.
...
llvm-svn: 15447
2004-08-03 20:23:44 +00:00
Misha Brukman
10a585beaf
* Use simpler instruction templates to define instructions
...
* Fix several extended opcodes
llvm-svn: 15423
2004-08-02 21:58:52 +00:00
Misha Brukman
f2119a5b6f
Separate instruction formats from instruction definitions.
...
llvm-svn: 15414
2004-08-02 16:54:54 +00:00
Misha Brukman
148ad01de1
Renamed files:
...
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
llvm-svn: 15295
2004-07-27 23:29:16 +00:00
Misha Brukman
8c047d4fad
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
...
llvm-svn: 15283
2004-07-27 18:35:54 +00:00
Misha Brukman
93b0ea58a2
MovePCtoLR (which is `bl' in disguise) modifies LR implicitly
...
llvm-svn: 15272
2004-07-27 17:15:05 +00:00
Misha Brukman
3d395cbda3
Add SUBI instruction
...
llvm-svn: 15077
2004-07-21 15:53:04 +00:00
Misha Brukman
f47940855d
Differentiate between global and weak symbol loads
...
llvm-svn: 15037
2004-07-20 15:52:25 +00:00
Misha Brukman
f93e5532d5
Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman
...
llvm-svn: 14895
2004-07-16 20:33:41 +00:00
Misha Brukman
efcb6b8c2c
* Coalesce the handy CALL* alias opcodes with the standard ones
...
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls
llvm-svn: 14511
2004-06-30 22:00:45 +00:00
Misha Brukman
2242e8d27f
* Use LA instead of LWZ for LoadLoAddr
...
* Specify the isCall bit and caller-save registers for some call instrs
llvm-svn: 14501
2004-06-29 23:37:36 +00:00
Misha Brukman
92cc94a0e5
Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman.
...
llvm-svn: 14470
2004-06-28 18:27:08 +00:00
Misha Brukman
2f7332b752
Set isBranch and isTerminator bits on all branch instructions.
...
llvm-svn: 14469
2004-06-28 18:23:35 +00:00
Misha Brukman
269034c151
Initial revision
...
llvm-svn: 14283
2004-06-21 16:55:25 +00:00