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3169 Commits

Author SHA1 Message Date
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Duncan Sands
ed2ef5a987 Correct some bogus target triples. 
llvm-svn: 103265
 2010-05-07 17:03:48 +00:00
Nick Lewycky
3e5720a898 Revert r103133 and add testcase from PR7066. 
llvm-svn: 103233
 2010-05-07 01:45:38 +00:00
Dan Gohman
f863ad3dc5 Disable the new unknown-location code for now. It causes a major 
increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226
 2010-05-07 01:08:53 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Dan Gohman
3190e5c292 Add a testcase for r103135, explicitly representing unknown 
locations in debug line info.

llvm-svn: 103189
 2010-05-06 17:49:17 +00:00
Chris Lattner
014a954e3d Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed. 
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140
 2010-05-06 00:05:37 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jakob Stoklund Olesen
2e5d12acfa Fix PR6520. An earlyclobber physreg must not be allocated to anything else. 
llvm-svn: 103133
 2010-05-05 23:07:41 +00:00
Jim Grosbach
7eb0b4d646 fix copy/paste oops. 
llvm-svn: 103122
 2010-05-05 21:07:46 +00:00
Jim Grosbach
25fc725b2a Add tests for ARMV7M divide instruction use 
llvm-svn: 103120
 2010-05-05 20:47:15 +00:00
Jim Grosbach
9b7ae2027f remove unneeded underscores. 
llvm-svn: 103114
 2010-05-05 19:55:58 +00:00
Jim Grosbach
7ea67d346f Convert to filecheck 
llvm-svn: 103113
 2010-05-05 19:41:11 +00:00
Chris Lattner
b4696853af "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'." 
Patch by Kalle Raiskila!

llvm-svn: 103021
 2010-05-04 17:58:46 +00:00
Dale Johannesen
b10ca6bf4c Implement builtin_return_address(x) and builtin_frame_address(x) 
on PPC for x!=0.  7624113.

llvm-svn: 102972
 2010-05-03 22:59:34 +00:00
Jakob Stoklund Olesen
51ab2653d5 Check that subregisters don't have independent values in RemoveCopyByCommutingDef(). 
This fixes PR6941.

llvm-svn: 102970
 2010-05-03 22:40:32 +00:00
Dan Gohman
c024fd43c9 Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul, 
when the type is floating-point.

llvm-svn: 102969
 2010-05-03 22:36:46 +00:00
Dan Gohman
15cb983f55 Fix a bug which prevented tail merging of return instructions in 
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.

The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.

Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.

And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.

llvm-svn: 102907
 2010-05-03 14:35:47 +00:00
Duncan Sands
153ad3b903 Remove the -enable-sjlj-eh option, which doesn't do anything. 
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.

llvm-svn: 102865
 2010-05-02 15:36:26 +00:00
Anton Korobeynikov
a3726088fa Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), 
when needed. This fixes PR7001

llvm-svn: 102838
 2010-05-01 12:52:34 +00:00
Anton Korobeynikov
f31181a0cc Do folding for indirect branches, where possible 
llvm-svn: 102836
 2010-05-01 12:28:21 +00:00
Anton Korobeynikov
9b724bd446 Implement indirect branches on MSP430 
llvm-svn: 102835
 2010-05-01 12:04:32 +00:00
Bill Wendling
7b6527b94b Test failing too much on too many platforms. 
llvm-svn: 102812
 2010-05-01 00:12:33 +00:00
Bill Wendling
a348ff69b8 Maybe it needs sse2? 
llvm-svn: 102802
 2010-04-30 23:19:29 +00:00
Bill Wendling
d1c5f11f72 Force 64-bit. 
llvm-svn: 102800
 2010-04-30 22:45:20 +00:00
Bill Wendling
95a4929ac7 EXTRACT_VECTOR_ELT of an INSERT_VECTOR_ELT may have the same index, but the 
indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.

llvm-svn: 102791
 2010-04-30 22:19:17 +00:00
Jakob Stoklund Olesen
fac584ed9e The local register allocator has to spill dirty callee saved registers before a 
call that might throw. The landing pad assumes that all registers are in stack
slots.

We used to spill those dirty CSRs after the call, and the stack slots would be
wrong when arriving at the landing pad.

llvm-svn: 102770
 2010-04-30 21:19:29 +00:00
Evan Cheng
fc86d7fbdc Fix test. 
llvm-svn: 102694
 2010-04-30 06:00:56 +00:00
Evan Cheng
9303b11e47 Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way. 
llvm-svn: 102683
 2010-04-30 01:12:32 +00:00
Jakob Stoklund Olesen
01254ea96d Reject really weird coalescer case when trying to merge identical subregisters 
of different register classes. e.g.

  %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3

Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.

This should unbreak the dragonegg builder.

llvm-svn: 102672
 2010-04-29 23:47:46 +00:00
Evan Cheng
da89f22f3d Load folding tail call should not use ebp / rbp after it's popped. PEI 
should use esp / rsp to reference frame instead.

llvm-svn: 102596
 2010-04-29 05:08:22 +00:00
Chris Lattner
9867c1a075 Rework global alignment computation again. Now we do round up 
alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).

llvm-svn: 102515
 2010-04-28 19:58:07 +00:00
Evan Cheng
d4fe387eb8 Enable i16 to i32 promotion by default. 
llvm-svn: 102493
 2010-04-28 08:30:49 +00:00
Evan Cheng
08e5f737d2 Update tests. 
llvm-svn: 102487
 2010-04-28 01:53:13 +00:00
Devang Patel
570e9d53a7 Emit debug info for byval parameters. 
llvm-svn: 102486
 2010-04-28 01:39:28 +00:00
Evan Cheng
2aaefc6167 Do not count kill, implicit_def instructions as printed instructions. 
llvm-svn: 102453
 2010-04-27 19:38:45 +00:00
Chris Lattner
a9c1328501 round zero-byte .zerofill directives up to 1 byte. This 
should fix some "g++.dg-struct-layout-1" failures, 
rdar://7886017

llvm-svn: 102421
 2010-04-27 07:41:44 +00:00
Chris Lattner
9292bad5f5 on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400
 2010-04-26 23:37:21 +00:00
Bob Wilson
ece63716aa Handle register-to-register copies within the tGPR class. 
Radar 7896289

llvm-svn: 102396
 2010-04-26 23:20:08 +00:00
Dan Gohman
40561dd0ba When checking whether the special handling for an addrec increment which 
doesn't dominate the header is needed, don't check whether the increment
expression has computable loop evolution. While the operands of an
addrec are required to be loop-invariant, they're not required to 
dominate any part of the loop. This fixes PR6914.

llvm-svn: 102389
 2010-04-26 21:46:36 +00:00
Chris Lattner
4854eab087 fix PR6921 a different way. Intead of increasing the 
alignment of globals with a specified alignment, we fix
common variables to obey their alignment.  Add a comment
explaining why this behavior is important.

llvm-svn: 102365
 2010-04-26 18:46:46 +00:00
Chris Lattner
a8cd2ac893 Revert r102300/102301, which serious broke objc apps. 
llvm-svn: 102359
 2010-04-26 18:30:45 +00:00
Chris Lattner
e4a25eb35a Fix PR6921: globals were not getting correctly rounded up to their 
preferred alignment unless they were common or some other special
case.

llvm-svn: 102300
 2010-04-25 05:30:43 +00:00
Dan Gohman
42337e0ee9 Generalize LSR's OptimizeMax to handle the new kinds of max expressions 
that indvars may use, now that indvars is recognizing le and ge loops.

llvm-svn: 102235
 2010-04-24 03:13:44 +00:00
Stuart Hastings
85b5c330f2 Per Chris, fuse four trivial tests using grep (r102199) into one that uses FileCheck. 
llvm-svn: 102216
 2010-04-23 22:12:57 +00:00
Dan Gohman
6a48222bd8 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.

llvm-svn: 102206
 2010-04-23 19:41:15 +00:00
Stuart Hastings
ad81819149 Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
llvm-svn: 102199
 2010-04-23 19:03:32 +00:00
Dan Gohman
38949c2f1f Fix LSR to tolerate cases where ScalarEvolution initially 
misses an opportunity to fold add operands, but folds them
after LSR has separated them out. This fixes rdar://7886751.

llvm-svn: 102157
 2010-04-23 01:55:05 +00:00
Jim Grosbach
b9dccb6103 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.

llvm-svn: 102144
 2010-04-22 23:24:18 +00:00
Evan Cheng
a324da99ae Do not try to optimize a copy that has already been marked for deletion. 
llvm-svn: 102027
 2010-04-21 20:57:54 +00:00