Eli Friedman
b8c9f7ee35
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
...
FP_TO_XINT. Necessary for some cleanups I'm working on. Updated
from the previous version (r72431) to fix a bug and make some things a
bit clearer.
llvm-svn: 72445
2009-05-27 00:47:34 +00:00
Daniel Dunbar
75f52bda74
Back out r72431, it is causing a number of compilation crashes with clang.
...
llvm-svn: 72436
2009-05-26 21:27:02 +00:00
Stefanus Du Toit
031dcf315f
Update CPU capabilities for AMD machines
...
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
Eli Friedman
f7d0c01ed6
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
...
FP_TO_XINT. Necessary for some cleanups I'm working on.
llvm-svn: 72431
2009-05-26 19:18:56 +00:00
Chris Lattner
636bd70540
add some late optimizations that GCC does. It thinks these are a win
...
even on Core2, not just AMD processors which was a surprise to me.
llvm-svn: 72396
2009-05-25 20:28:19 +00:00
Chris Lattner
10cac1a776
fix typo
...
llvm-svn: 72395
2009-05-25 19:51:07 +00:00
Chris Lattner
60098b3e93
we should eventually add -march=atom and the new atom movbe instruction.
...
llvm-svn: 72387
2009-05-25 16:34:44 +00:00
Eli Friedman
fa8df9fa26
Make the PPC backend use a legal type for the operands to the BUILD_VECTOR
...
nodes it generates.
llvm-svn: 72356
2009-05-24 02:03:36 +00:00
Eli Friedman
f4d25bb2b6
Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the
...
moment.
llvm-svn: 72350
2009-05-23 22:44:52 +00:00
Anton Korobeynikov
1fe3d6d47b
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
...
llvm-svn: 72337
2009-05-23 19:51:43 +00:00
Anton Korobeynikov
c16f747585
Emit ARM Build Attributes
...
llvm-svn: 72336
2009-05-23 19:51:20 +00:00
Anton Korobeynikov
34fc85e2ee
Propagate CPU string out of SubtargetFeatures
...
llvm-svn: 72335
2009-05-23 19:50:50 +00:00
Eli Friedman
d877b76d14
Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit
...
systems instead of attempting to promote them to a 64-bit SINT_TO_FP or
FP_TO_SINT. This is in preparation for removing the type legalization
code from LegalizeDAG: once type legalization is gone from LegalizeDAG,
it won't be able to handle the i64 operand/result correctly.
This isn't quite ideal, but I don't think any other operation for any
target ends up in this situation, so treating this case specially seems
reasonable.
llvm-svn: 72324
2009-05-23 09:59:16 +00:00
Oscar Fuentes
832290edfe
CMake: Use libpthread in tblgen when needed. Updated list of source
...
files for PIC16 target.
llvm-svn: 72277
2009-05-22 20:55:15 +00:00
Bob Wilson
372984e7a2
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
...
for ARM. This fixes rdar://6908807.
llvm-svn: 72269
2009-05-22 17:38:41 +00:00
Sanjiv Gupta
07574e0dfa
Emit debug information for globals (which include automatic variables as well because on PIC16 they are emitted as globals by the frontend).
...
llvm-svn: 72262
2009-05-22 13:58:45 +00:00
Bob Wilson
0ac9317588
Minor formatting fixes.
...
llvm-svn: 72172
2009-05-20 16:30:25 +00:00
Evan Cheng
e17c02e328
Try again. Allow call to immediate address for ELF or when in static relocation mode.
...
llvm-svn: 72160
2009-05-20 04:53:57 +00:00
Evan Cheng
8a4887572e
Cannot use immediate as call absolute target in PIC mode.
...
llvm-svn: 72154
2009-05-20 01:11:00 +00:00
Bob Wilson
ba6b02b54b
Fix pr4227: Handle large immediate values in inline assembly.
...
llvm-svn: 72138
2009-05-19 21:27:57 +00:00
Bob Wilson
5e7a2b4ff8
Follow up on new support for memory operands in ARM inline assembly.
...
This fixes pr4233.
llvm-svn: 72115
2009-05-19 18:33:02 +00:00
Bob Wilson
c6726ecca5
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
...
the stack. Patch by Sandeep Patel.
llvm-svn: 72106
2009-05-19 10:02:36 +00:00
Bob Wilson
ec676a76e7
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
...
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
Dale Johannesen
b9a41be8b0
Spacing fix.
...
llvm-svn: 72083
2009-05-19 00:46:42 +00:00
Dale Johannesen
a0756109d8
Add OpSize to 16-bit ADC and SBB.
...
llvm-svn: 72045
2009-05-18 21:41:59 +00:00
Bob Wilson
51e9d81e72
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
...
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
llvm-svn: 72037
2009-05-18 20:55:32 +00:00
Dale Johannesen
6efc155312
Fill in the missing patterns for ADC and SBB.
...
Some comment cleanup.
llvm-svn: 72022
2009-05-18 17:44:15 +00:00
Anton Korobeynikov
85accafcba
Mark rotl/rotr as expand. This generates pretty ugly code, but this is better than nothing.
...
llvm-svn: 71976
2009-05-17 10:16:28 +00:00
Anton Korobeynikov
8753e89b79
Typo
...
llvm-svn: 71975
2009-05-17 10:15:22 +00:00
Jakob Stoklund Olesen
2a2fc7561b
Fix a missing def-flag on a Mips epilogue load.
...
llvm-svn: 71935
2009-05-16 07:26:06 +00:00
Jakob Stoklund Olesen
f416b4b5ce
Remember to set def-flag on register loaded from stack slot in CellSPU.
...
llvm-svn: 71934
2009-05-16 07:25:44 +00:00
Mike Stump
a25bd435de
Reflow to fit 80-col.
...
llvm-svn: 71813
2009-05-14 23:23:37 +00:00
Mike Stump
cd9198dd91
Reflow to fit 80-col.
...
llvm-svn: 71812
2009-05-14 23:22:47 +00:00
Jim Grosbach
bed3aeff20
Update the names of the exception handling sjlj instrinsics to
...
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
llvm-svn: 71758
2009-05-14 00:46:35 +00:00
Jim Grosbach
024feec42e
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
...
llvm-svn: 71735
2009-05-13 22:32:43 +00:00
Evan Cheng
9bd08f0cde
Run code placement optimization for targets that want it (arm and x86 for now).
...
llvm-svn: 71726
2009-05-13 21:42:09 +00:00
Bill Wendling
e421c8f63d
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
...
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
llvm-svn: 71722
2009-05-13 21:33:08 +00:00
Sanjiv Gupta
ad40927f6a
Run through the list of globals once and sectionize all types of globlas includeing declarations. Later emit them from their section lists.
...
llvm-svn: 71661
2009-05-13 15:13:17 +00:00
Dale Johannesen
18cc7c12b7
Add an int64_t variant of abs, for host environments
...
without one. Use it where we were using abs on
int64_t objects.
(I strongly suspect the casts to unsigned in the
fragments in LoopStrengthReduce are not doing whatever
the original intent was, but the obvious change to
uint64_t doesn't work. Maybe later.)
llvm-svn: 71612
2009-05-13 00:24:22 +00:00
Jim Grosbach
4bb5e9d1df
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
...
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
llvm-svn: 71610
2009-05-12 23:59:14 +00:00
Jim Grosbach
4861b683a8
correct register class for tADDspi to GPR since the register will always be SP
...
llvm-svn: 71602
2009-05-12 22:30:18 +00:00
Bill Wendling
a6f172b0f2
More MSVC fixes -- class/struct conflicts.
...
llvm-svn: 71601
2009-05-12 21:55:29 +00:00
Evan Cheng
7f78e63cf3
80 col violations.
...
llvm-svn: 71582
2009-05-12 20:17:52 +00:00
Bob Wilson
5a9381d75f
Fix up a few minor typos in comments.
...
llvm-svn: 71563
2009-05-12 17:35:29 +00:00
Bob Wilson
de6e2f9bf0
Fix 80-col violations and remove trailing whitespace. No functional changes.
...
llvm-svn: 71562
2009-05-12 17:09:30 +00:00
Sanjiv Gupta
b1a0a4a7f5
Iterate over globals once and sectionize them into appropriate sections.
...
Later in asmprinter, go over thsese sections and print them.
Do not print empty sections.
llvm-svn: 71560
2009-05-12 17:07:27 +00:00
Sanjiv Gupta
ead0ba2ea0
We do not need to create a label for external defs and decls,
...
just emit a comment for readability.
llvm-svn: 71544
2009-05-12 06:52:41 +00:00
Sanjiv Gupta
e60e9f8c0b
Mark mayLoad, mayStore for insns correctly and use them
...
to check if an insn is accessing memory during mem sel optimization.
llvm-svn: 71537
2009-05-12 04:30:38 +00:00
Dan Gohman
d13f674130
Factor the code for collecting IV users out of LSR into an IVUsers class,
...
and generalize it so that it can be used by IndVarSimplify. Implement the
base IndVarSimplify transformation code using IVUsers. This removes
TestOrigIVForWrap and associated code, as ScalarEvolution now has enough
builtin overflow detection and folding logic to handle all the same cases,
and more. Run "opt -iv-users -analyze -disable-output" on your favorite
loop for an example of what IVUsers does.
This lets IndVarSimplify eliminate IV casts and compute trip counts in
more cases. Also, this happens to finally fix the remaining testcases
in PR1301.
Now that IndVarSimplify is being more aggressive, it occasionally runs
into the problem where ScalarEvolutionExpander's code for avoiding
duplicate expansions makes it difficult to ensure that all expanded
instructions dominate all the instructions that will use them. As a
temporary measure, IndVarSimplify now uses a FixUsesBeforeDefs function
to fix up instructions inserted by SCEVExpander. Fortunately, this code
is contained, and can be easily removed once a more comprehensive
solution is available.
llvm-svn: 71535
2009-05-12 02:17:14 +00:00
Evan Cheng
96cd1decc6
Avoid unneeded SIB byte encoding. Patch by Zoltan Varga.
...
llvm-svn: 71520
2009-05-12 00:07:35 +00:00
Jay Foad
2842dd918b
Don't #include DerivedTypes.h from TargetData.h.
...
llvm-svn: 71468
2009-05-11 19:38:09 +00:00
Dan Gohman
2060db5db5
Fix two wording errors that Duncan spotted.
...
llvm-svn: 71459
2009-05-11 18:51:16 +00:00
Dan Gohman
361dcef406
LLVM has unaligned loads and stores now.
...
llvm-svn: 71449
2009-05-11 18:06:05 +00:00
Dan Gohman
d365c7a5a3
Upgrade this example to new-style syntax.
...
llvm-svn: 71447
2009-05-11 18:04:52 +00:00
Dan Gohman
0edabc8a6f
Convert a subtract into a negate and an add when it helps x86
...
address folding.
llvm-svn: 71446
2009-05-11 18:02:53 +00:00
Chris Lattner
f5f153394d
remove some done things: we have nocapture and SROA is smarter.
...
llvm-svn: 71443
2009-05-11 17:41:40 +00:00
Chris Lattner
d50058b0c0
add a note
...
llvm-svn: 71442
2009-05-11 17:36:33 +00:00
Jay Foad
d8149f17c2
Change TargetData::getIntPtrType() to return an IntegerType instead of
...
just a Type.
llvm-svn: 71426
2009-05-11 11:13:47 +00:00
Sanjiv Gupta
264cfd0017
Fix more naming issues.
...
compiler libcalls start with .lib. now.
fixed section names.
llvm-svn: 71424
2009-05-11 08:52:04 +00:00
Sanjiv Gupta
0506627b14
Detect calls to compiler intrinsics and emit an extern declarations
...
only for those. These extern declarations to intrinsics are currently
being emitted at the bottom of generated .s file, which works fine with
gpasm(not sure about MPSAM though).
PIC16 linker generates errors for few cases (function-args/struct_args_5) if you do not include any
extern declarations (even if no intrinsics are being used), but that
needs to be fixed in the linker itself.
llvm-svn: 71423
2009-05-11 06:01:38 +00:00
Sanjiv Gupta
03acc3e940
Module iterator contains list of filescope functions as well, we don't need to emit and global declarations for them. This was working earlier and was broken during one of the recent commit for PIC16 naming.
...
llvm-svn: 71394
2009-05-10 16:18:39 +00:00
Anton Korobeynikov
02d9c5b905
Add imm-reg and imm-mem patters for cmp on msp430
...
(imm is allowed to be source operand, not dest...)
llvm-svn: 71393
2009-05-10 14:49:00 +00:00
Sanjiv Gupta
07c4b65112
Changed lowering and asmprinter to use ABI Names class called PAN.
...
llvm-svn: 71386
2009-05-10 05:23:47 +00:00
Eli Friedman
69845a85a5
Remove a completed optimization. Add a potential optimization I ran
...
into.
llvm-svn: 71352
2009-05-09 08:40:15 +00:00
Duncan Sands
f7af13b2d4
Rename PaddedSize to AllocSize, in the hope that this
...
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
llvm-svn: 71349
2009-05-09 07:06:46 +00:00
Sanjiv Gupta
65a3fde6a5
Use 16 bit arithmetic while retrieving the address of callee's frame during indirect function calls, and set pclath before every call to retrieve the frame address.
...
llvm-svn: 71323
2009-05-09 05:11:19 +00:00
Evan Cheng
8e26879521
PPC::B and PPC::BCC's target operand may be an immediate.
...
llvm-svn: 71282
2009-05-08 23:09:25 +00:00
Anton Korobeynikov
b3dc881070
Factor out cycle-finder code and make it generic.
...
llvm-svn: 71241
2009-05-08 18:51:58 +00:00
Anton Korobeynikov
5461d8e07d
Allow 8 bit select in custom inserter
...
llvm-svn: 71239
2009-05-08 18:51:21 +00:00
Anton Korobeynikov
1be416b310
Expand UREM / SREM into libcalls
...
llvm-svn: 71236
2009-05-08 18:50:41 +00:00
Anton Korobeynikov
8364529d37
Add 8 bit select
...
llvm-svn: 71235
2009-05-08 18:50:26 +00:00
Chris Lattner
7b2dabcac9
Fix PR4152: asm constraint validation happens before dag combine, so we
...
need to work a bit to combine things like (x+c1+c2) into x+c3.
llvm-svn: 71232
2009-05-08 18:23:14 +00:00
Evan Cheng
2a1d20b0fb
Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.
...
/// A:
/// ...
/// <fallthrough to B>
///
/// B: --> loop header
/// ...
/// jcc <cond> C, [exit]
///
/// C:
/// ...
/// jmp B
///
/// ==>
///
/// A:
/// ...
/// jmp B
///
/// C: --> new loop header
/// ...
/// <fallthough to B>
///
/// B:
/// ...
/// jcc <cond> C, [exit]
llvm-svn: 71209
2009-05-08 06:34:09 +00:00
Nick Lewycky
575cf1d259
Add missing #include for "strlen" which is used inline in this header. Fixes
...
build under gcc 4.3.
llvm-svn: 71208
2009-05-08 06:22:25 +00:00
Sanjiv Gupta
3a905e7586
Moved pic16 naming functions to correct place.
...
No functionality change.
llvm-svn: 71207
2009-05-08 04:50:14 +00:00
Evan Cheng
1109c5103e
Eliminate compiler warnings.
...
llvm-svn: 71149
2009-05-07 05:31:56 +00:00
Oscar Fuentes
a06115b0ab
CMake: Updated lib/Target/PIC16/CMakeLists.txt.
...
llvm-svn: 71115
2009-05-06 20:40:05 +00:00
Dale Johannesen
b2cf4944c2
Use X86AddrNumOperands instead of magic constant one
...
more place. This fixes a bunch of x86-64 JIT regressions.
(Introduced when the value of the magic constant changed
in 68645. At the time apparently nobody noticed; failures
were hidden in 70343-70439 by an unrelated bug, so showed
up again as "new" failures in 70440.)
llvm-svn: 71106
2009-05-06 19:04:30 +00:00
Sanjiv Gupta
cc6f71e64c
Emit banksel and movlp instructions.
...
Split large global data (both initialized and un-initialized) into multiple sections of <= 80 bytes.
Provide routines to manage PIC16 ABI naming conventions.
llvm-svn: 71073
2009-05-06 08:02:01 +00:00
Chris Lattner
5cc9a36d1c
Add basic support for code generation of
...
addrspace(257) -> FS relative on x86. Patch by Zoltan Varga!
llvm-svn: 70992
2009-05-05 18:52:19 +00:00
Evan Cheng
138eed76c7
Revert part of 70929 that has to do with determining whether a SIB byte is needed. It causes a lot of x86_64 JIT failures.
...
llvm-svn: 70986
2009-05-05 18:18:57 +00:00
Evan Cheng
95ce4ffb36
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
...
llvm-svn: 70950
2009-05-05 00:30:09 +00:00
Evan Cheng
6843d3293b
- Avoid the longer SIB encoding on x86_64 when it's not needed.
...
- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp
Patch by Zoltan Varga.
llvm-svn: 70929
2009-05-04 22:49:16 +00:00
Dan Gohman
2973567a95
X86FastISel doesn't support the -tailcallopt ABI.
...
llvm-svn: 70902
2009-05-04 19:50:33 +00:00
Anton Korobeynikov
262a397978
Fix code emission for conditional branches.
...
Patch by Collin Winter!
llvm-svn: 70898
2009-05-04 19:10:38 +00:00
Dan Gohman
83dfa97326
Trim unnecessary #includes.
...
llvm-svn: 70880
2009-05-04 17:11:06 +00:00
Anton Korobeynikov
df33e5a803
Handle implicit zext in a better way. Shamelessly stolen from x86 backend.
...
Thanks for Dan Gohman for suggestion!
llvm-svn: 70782
2009-05-03 15:50:18 +00:00
Anton Korobeynikov
46a92ec4d6
Update due to mainline API change
...
llvm-svn: 70769
2009-05-03 13:19:42 +00:00
Anton Korobeynikov
13ed1c4514
Add TODO list :)
...
llvm-svn: 70768
2009-05-03 13:19:24 +00:00
Anton Korobeynikov
8988fea464
Make handling of conditional stuff much more straightforward
...
llvm-svn: 70767
2009-05-03 13:19:09 +00:00
Anton Korobeynikov
d8c42b2dee
Temporary disable imm patterns for cmp. Actually, all cmp-related stuff (select_cc, setcc, br_cc). needs to be rethought
...
llvm-svn: 70766
2009-05-03 13:18:50 +00:00
Anton Korobeynikov
e6c8cc6c51
Expand divisions into libcalls
...
llvm-svn: 70765
2009-05-03 13:18:33 +00:00
Anton Korobeynikov
54bbd77498
Custom lower SIGN_EXTEND
...
llvm-svn: 70763
2009-05-03 13:17:49 +00:00
Anton Korobeynikov
9103796e69
Some eye-candy
...
llvm-svn: 70762
2009-05-03 13:17:31 +00:00
Anton Korobeynikov
c0ea294fb9
Print function header / footer
...
llvm-svn: 70761
2009-05-03 13:17:11 +00:00
Anton Korobeynikov
f4b4812c83
Fix printing: je => jeq
...
llvm-svn: 70760
2009-05-03 13:16:54 +00:00
Anton Korobeynikov
4b5232c990
Add 8bit shifts
...
llvm-svn: 70759
2009-05-03 13:16:37 +00:00
Anton Korobeynikov
d0e3939bdf
Handle logical shift right (at least I hope so :) )
...
llvm-svn: 70758
2009-05-03 13:16:17 +00:00
Anton Korobeynikov
7dd27f2e41
Handle anyext
...
llvm-svn: 70757
2009-05-03 13:15:57 +00:00
Anton Korobeynikov
baf9278166
Expand all sorts of indirect branches
...
llvm-svn: 70755
2009-05-03 13:15:40 +00:00
Anton Korobeynikov
806b8efb5e
Add InsertBranch() hook for tail mergeing
...
llvm-svn: 70754
2009-05-03 13:15:22 +00:00
Anton Korobeynikov
b97b120cf9
Implement bswap
...
llvm-svn: 70753
2009-05-03 13:15:03 +00:00
Anton Korobeynikov
cebc97d79c
Properly handle ExternalSymbol's
...
llvm-svn: 70752
2009-05-03 13:14:46 +00:00
Anton Korobeynikov
9b84c6b633
Expand muls (all mulls!) to libcalls for now
...
llvm-svn: 70751
2009-05-03 13:14:25 +00:00
Anton Korobeynikov
80d0bdc789
Provide addc and subc
...
llvm-svn: 70748
2009-05-03 13:13:34 +00:00
Anton Korobeynikov
1f80bde7ad
Add left shift
...
llvm-svn: 70747
2009-05-03 13:13:17 +00:00
Anton Korobeynikov
d9b4143e47
Add direct branch
...
llvm-svn: 70746
2009-05-03 13:12:58 +00:00
Anton Korobeynikov
c5a13f6a3f
It's error-prone to maintain two separate variants of asmprinting stuff, one of which is even used. Drop second (aka 'intel') variant of operands. It can be added later, if needed.
...
llvm-svn: 70745
2009-05-03 13:12:37 +00:00
Anton Korobeynikov
f7943f8df6
Lower select with custom inserted and make condjumps generic
...
llvm-svn: 70744
2009-05-03 13:12:23 +00:00
Anton Korobeynikov
d55d6586ae
Add first draft for conditions, conditional branches, etc
...
llvm-svn: 70743
2009-05-03 13:12:06 +00:00
Anton Korobeynikov
2b8085a3f5
Hanle i8 returns
...
llvm-svn: 70742
2009-05-03 13:11:48 +00:00
Anton Korobeynikov
67b1a5c20b
Small tweaking
...
llvm-svn: 70741
2009-05-03 13:11:35 +00:00
Anton Korobeynikov
c428224a89
Add prologue/epilogue emission. Fix frame pointer handling.
...
llvm-svn: 70740
2009-05-03 13:11:20 +00:00
Anton Korobeynikov
10d199fa80
Add code for save/restore of callee-saved registers
...
llvm-svn: 70739
2009-05-03 13:11:04 +00:00
Anton Korobeynikov
6a63537ff0
Two more hooks for RA and FP registers
...
llvm-svn: 70738
2009-05-03 13:10:40 +00:00
Anton Korobeynikov
06d645c199
Proper handle loading of effective address of stack slot stuff
...
llvm-svn: 70737
2009-05-03 13:10:26 +00:00
Anton Korobeynikov
88cc152a78
Match frame indexes
...
llvm-svn: 70736
2009-05-03 13:10:11 +00:00
Anton Korobeynikov
e7639579a3
First draft of stack slot loads / stores lowering
...
llvm-svn: 70735
2009-05-03 13:09:57 +00:00
Anton Korobeynikov
1f9d4dc64d
Reverse order of memory arguments
...
llvm-svn: 70734
2009-05-03 13:09:40 +00:00
Anton Korobeynikov
f3fadcbbda
Remove bogus pattern
...
llvm-svn: 70733
2009-05-03 13:09:24 +00:00
Anton Korobeynikov
47c1450013
Correct asmprinting of memory operands
...
llvm-svn: 70732
2009-05-03 13:09:10 +00:00
Anton Korobeynikov
eea3a58bbf
Match wrapper node for address
...
llvm-svn: 70731
2009-05-03 13:08:51 +00:00
Anton Korobeynikov
cd06be1d13
Add lowering for global address nodes. Not pretty efficient though.
...
llvm-svn: 70730
2009-05-03 13:08:33 +00:00
Anton Korobeynikov
e02a674ee0
Some early full call lowering draft for direct calls
...
llvm-svn: 70729
2009-05-03 13:08:13 +00:00
Anton Korobeynikov
b396742d02
Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
...
llvm-svn: 70728
2009-05-03 13:07:54 +00:00
Anton Korobeynikov
4fa710b300
Add CALL lowering.
...
llvm-svn: 70727
2009-05-03 13:07:31 +00:00
Anton Korobeynikov
582d2a335b
Add bunch of mem-whatever patterns
...
llvm-svn: 70726
2009-05-03 13:07:10 +00:00
Anton Korobeynikov
d14ee9eeae
Add bunch of reg-mem inst patterns
...
llvm-svn: 70725
2009-05-03 13:06:46 +00:00
Anton Korobeynikov
7b7a743ea8
Add normal and trunc stores
...
llvm-svn: 70724
2009-05-03 13:06:26 +00:00
Anton Korobeynikov
91359dcc3b
Basic support for mem=>reg moves
...
llvm-svn: 70723
2009-05-03 13:06:03 +00:00
Anton Korobeynikov
83122b7ef0
Add 8-bit insts. zext behaviour is not modelled yet
...
llvm-svn: 70722
2009-05-03 13:05:42 +00:00
Anton Korobeynikov
1c0af22261
Add 8-bit regclass and pattern for sext_inreg
...
llvm-svn: 70721
2009-05-03 13:05:22 +00:00
Anton Korobeynikov
d74b7ab46d
Add pattern for OR
...
llvm-svn: 70720
2009-05-03 13:05:00 +00:00
Anton Korobeynikov
aff90ae4f2
Add reg-imm variants
...
llvm-svn: 70719
2009-05-03 13:04:41 +00:00
Anton Korobeynikov
ff4332fcde
Add hint to nop
...
llvm-svn: 70718
2009-05-03 13:04:23 +00:00
Anton Korobeynikov
a46b46fa46
Add more instructions
...
llvm-svn: 70717
2009-05-03 13:04:06 +00:00
Anton Korobeynikov
1921caf185
Cleanup
...
llvm-svn: 70716
2009-05-03 13:03:50 +00:00
Anton Korobeynikov
262c4b9ff9
Add dummy lowering for shifts
...
llvm-svn: 70715
2009-05-03 13:03:33 +00:00
Anton Korobeynikov
f21d1d0d2c
We don't have any div at all - thus mark it as expensive
...
llvm-svn: 70714
2009-05-03 13:03:14 +00:00
Anton Korobeynikov
df71fb8a3a
We're not going to spend 100% of time in interrupts, do we? :)
...
llvm-svn: 70713
2009-05-03 13:02:57 +00:00
Anton Korobeynikov
627e169e8e
Add simple reg-reg add.
...
llvm-svn: 70712
2009-05-03 13:02:39 +00:00
Anton Korobeynikov
be8018ff1d
gas uses lower letter for register names
...
llvm-svn: 70711
2009-05-03 13:02:22 +00:00
Anton Korobeynikov
e9e0353b21
Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
...
llvm-svn: 70710
2009-05-03 13:02:04 +00:00
Anton Korobeynikov
8b763cb6ec
Add function body printing routine
...
llvm-svn: 70709
2009-05-03 13:01:41 +00:00
Anton Korobeynikov
5f8e2ee553
Add 'msp430' target triple recognizer
...
llvm-svn: 70708
2009-05-03 13:01:23 +00:00
Anton Korobeynikov
f5317831da
Make emit{Prologue,Epilogue}() noop for now
...
llvm-svn: 70707
2009-05-03 13:01:04 +00:00
Anton Korobeynikov
57d55e96cd
Add callee-saved regs & reg classes getter hooks
...
llvm-svn: 70706
2009-05-03 13:00:46 +00:00
Anton Korobeynikov
70dbb3eb2f
Add simple FP indicator for given function hook
...
llvm-svn: 70705
2009-05-03 13:00:28 +00:00
Anton Korobeynikov
4c91b3a6f2
Provide set of reserved registers
...
llvm-svn: 70704
2009-05-03 13:00:11 +00:00
Anton Korobeynikov
ebab62b827
Add proper ISD::RET lowering
...
llvm-svn: 70703
2009-05-03 12:59:50 +00:00
Anton Korobeynikov
e74a06c068
Add first draft of MSP430 calling convention stuff and draft of ISD::FORMAL_ARGUMENTS node lowering.
...
llvm-svn: 70702
2009-05-03 12:59:33 +00:00
Anton Korobeynikov
b85740bf76
Fix register names, fix register allocation order, handle frame pointer.
...
llvm-svn: 70701
2009-05-03 12:59:16 +00:00
Anton Korobeynikov
5af68b43bc
Clearify the usage and add some debug stuff
...
llvm-svn: 70700
2009-05-03 12:58:58 +00:00
Anton Korobeynikov
840e251a16
Cleanup
...
llvm-svn: 70699
2009-05-03 12:58:40 +00:00
Anton Korobeynikov
372921c7be
Add cmake script. No idea whether it works or not :)
...
llvm-svn: 70698
2009-05-03 12:58:22 +00:00
Anton Korobeynikov
0eec6e6c0a
Add a note
...
llvm-svn: 70697
2009-05-03 12:58:05 +00:00
Anton Korobeynikov
be51fd1388
Typo
...
llvm-svn: 70695
2009-05-03 12:57:47 +00:00
Anton Korobeynikov
d49e584da5
Dummy MSP430 backend
...
llvm-svn: 70694
2009-05-03 12:57:15 +00:00
Chris Lattner
c6d561ed27
'The attached patch fixes an issue where llc -march=cpp fails with
...
"Invalid primitive type" on input containing the x86_fp80 type.'
Patch by Collin Winter!
llvm-svn: 70610
2009-05-01 23:54:26 +00:00
Argyrios Kyrtzidis
123a0fb56f
Fix compilation for some targets other than x86.
...
llvm-svn: 70522
2009-04-30 23:50:26 +00:00
Argyrios Kyrtzidis
9956976b76
Make DebugLoc independent of DwarfWriter.
...
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)
llvm-svn: 70520
2009-04-30 23:22:31 +00:00
Jakob Stoklund Olesen
bcb5d651a3
getCommonSubClass() - Calculate the largest common sub-class of two register
...
classes.
This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.
llvm-svn: 70512
2009-04-30 21:23:32 +00:00
Dan Gohman
8a0e27efb2
Set mayLoad on MOVZX32_NOREXrm8 too.
...
llvm-svn: 70466
2009-04-30 03:11:48 +00:00
Evan Cheng
b7d41a6680
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
...
llvm-svn: 70461
2009-04-30 00:58:57 +00:00
Chris Lattner
25991c4e7d
remove progname which is never set. PR4085
...
llvm-svn: 70453
2009-04-30 00:24:33 +00:00
Bill Wendling
40a162f75f
Instead of passing in an unsigned value for the optimization level, use an enum,
...
which better identifies what the optimization is doing. And is more flexible for
future uses.
llvm-svn: 70440
2009-04-29 23:29:43 +00:00
Nate Begeman
b407809122
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
...
llvm-svn: 70425
2009-04-29 22:47:44 +00:00
Nate Begeman
414534b3eb
Implement review feedback for vector shuffle work.
...
llvm-svn: 70372
2009-04-29 05:20:52 +00:00
Sanjiv Gupta
b1c777e865
Add a public method called getAddressSpace() to the GlobalAddressSDNode.
...
llvm-svn: 70366
2009-04-29 04:43:24 +00:00
Bill Wendling
7546bed590
Second attempt:
...
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
llvm-svn: 70343
2009-04-29 00:15:41 +00:00
Anton Korobeynikov
1799ac4b55
Properly print 'P' modifier on inline asm memory operands.
...
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!
llvm-svn: 70328
2009-04-28 21:49:33 +00:00
Sanjiv Gupta
19e7fe61ce
GlobalValue is always pointer type, so an assert isn't required.
...
llvm-svn: 70300
2009-04-28 16:39:45 +00:00
Bill Wendling
ef47ace92f
r70270 isn't ready yet. Back this out. Sorry for the noise.
...
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
Bill Wendling
2799e916c3
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
...
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
llvm-svn: 70270
2009-04-28 00:21:31 +00:00
Nate Begeman
9d121924fd
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
...
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
llvm-svn: 70225
2009-04-27 18:41:29 +00:00
Dan Gohman
a241dec2fc
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
...
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!
Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.
llvm-svn: 70211
2009-04-27 16:41:36 +00:00
Dan Gohman
180fa04e35
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
...
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.
llvm-svn: 70210
2009-04-27 16:33:14 +00:00
Dan Gohman
885b9c3688
Break up long multi-mnemonic strings into separate lines for readability.
...
llvm-svn: 70209
2009-04-27 15:13:28 +00:00
Mon P Wang
904d654436
Revised 68749 to allow matching of load/stores for address spaces < 256.
...
llvm-svn: 70197
2009-04-27 07:22:10 +00:00
Chris Lattner
b47e34ac59
add support for detecting process features on win64, patch by
...
Nicolas Capens!
llvm-svn: 70057
2009-04-25 18:27:23 +00:00
Bob Wilson
162870a4b3
Change LowerCallResult method so that CCValAssign::BCvt can be used with
...
f64 types. This is not used for anything yet.
llvm-svn: 70006
2009-04-25 00:33:20 +00:00
Bob Wilson
0ac8a0cf95
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
...
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
llvm-svn: 69978
2009-04-24 17:05:01 +00:00
Bob Wilson
2a47f01759
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
...
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
llvm-svn: 69977
2009-04-24 17:00:36 +00:00
Bob Wilson
1067abd956
Remove unnecessary references to f32 types. After specifying that f32
...
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
llvm-svn: 69973
2009-04-24 16:55:25 +00:00
Rafael Espindola
4e7a0bf1f1
Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
...
very elegant, but neither is the tls specification :-(
llvm-svn: 69968
2009-04-24 12:59:40 +00:00
Rafael Espindola
0b1037ad26
Revert 69952. Causes testsuite failures on linux x86-64.
...
llvm-svn: 69967
2009-04-24 12:40:33 +00:00
Nate Begeman
c1a09c7dfa
PR2957
...
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
llvm-svn: 69952
2009-04-24 03:42:54 +00:00
Dan Gohman
46ab8008a8
Fix spurious indentation in a comment.
...
llvm-svn: 69934
2009-04-23 22:41:05 +00:00
Sanjiv Gupta
0457bf4420
Banksel immediate constant will always immediately follow the GA/ES, so scan an insn from beginnin to find out the banksel operand.
...
llvm-svn: 69883
2009-04-23 10:34:58 +00:00
Dan Gohman
6a4629e856
Add support for printing MO_ExternalSymbol operands in
...
memory operand tuples. This doesn't ever come up in normal
code however.
llvm-svn: 69848
2009-04-23 00:57:37 +00:00
Sanjiv Gupta
60c6705684
Make the function begin label start after ther data pointer.
...
The address of data frame for function can be obtained by subtracting 2 from the function begin label.
llvm-svn: 69801
2009-04-22 12:02:36 +00:00
Duncan Sands
58c9c564a9
Get rid of what looks like a copy-and-pasted typo.
...
Spotted by gcc-4.5.
llvm-svn: 69673
2009-04-21 09:44:39 +00:00
Rafael Espindola
5adc7ad39e
TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.
...
This fixes PR4002.
llvm-svn: 69672
2009-04-21 08:22:09 +00:00
Sanjiv Gupta
30ea654901
Handle direct aggregate type arguments.
...
llvm-svn: 69665
2009-04-21 05:54:51 +00:00
Dan Gohman
de72d5129b
Make X86's copyRegToReg able to handle copies to and from subclasses.
...
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.
llvm-svn: 69635
2009-04-20 22:54:34 +00:00
Daniel Dunbar
6326c97515
Remove unused variable.
...
llvm-svn: 69624
2009-04-20 20:34:38 +00:00
Bob Wilson
f7e9ff1d28
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
...
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
llvm-svn: 69615
2009-04-20 18:36:57 +00:00
Devang Patel
64cae580dc
Match C backend only if it explicitly requested.
...
llvm-svn: 69613
2009-04-20 18:07:22 +00:00
Sanjiv Gupta
44b55dc966
Emit the auto variables of a function into a different section than parameters.
...
llvm-svn: 69605
2009-04-20 16:59:35 +00:00
Mon P Wang
4db825e615
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction
...
llvm-svn: 69417
2009-04-18 05:16:01 +00:00
Bill Wendling
0476a0acf3
Recommit r69335 and r69336. These were not causing problems.
...
llvm-svn: 69394
2009-04-17 22:40:38 +00:00
Bob Wilson
312344e025
Move the AddLiveIn function definition closer to its uses.
...
llvm-svn: 69382
2009-04-17 20:42:34 +00:00
Bob Wilson
b2ccd16655
Rearrange code to reduce indentation.
...
llvm-svn: 69381
2009-04-17 20:40:45 +00:00
Bob Wilson
911e92c7a3
Clean up formatting, remove trailing whitespace, fix comment typos and
...
punctuation. No functional changes.
llvm-svn: 69378
2009-04-17 20:35:10 +00:00
Bob Wilson
b8756b00cd
Use CallConvLower.h and TableGen descriptions of the calling conventions
...
for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
2009-04-17 19:07:39 +00:00
Rafael Espindola
d74132e2c5
For general dynamic TLS access we must use
...
leaq foo@TLSGD(%rip), %rdi
as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.
llvm-svn: 69350
2009-04-17 14:35:58 +00:00
Bill Wendling
073e1c91dd
Revert r69335 and r69336. They were causing build failures.
...
llvm-svn: 69347
2009-04-17 04:19:22 +00:00
Dan Gohman
d254f36e54
MOV8rr_NOREX is a "Move" instruction. This doesn't currently
...
matter, because this instruction isn't generated until after
things that care.
llvm-svn: 69336
2009-04-17 00:45:17 +00:00
Dan Gohman
2349973ff3
Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at
...
present, but it's inconsistent.
llvm-svn: 69335
2009-04-17 00:43:09 +00:00
Chris Lattner
d12470d85e
Fix some failures in targets on available_externally functions,
...
this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
llvm-svn: 69333
2009-04-17 00:26:12 +00:00
Rafael Espindola
a07d1c3103
fix PR3995. A scale must be 1, 2, 4 or 8.
...
llvm-svn: 69284
2009-04-16 12:34:53 +00:00
Dan Gohman
38bc0faa22
Fix 80-column violations.
...
llvm-svn: 69204
2009-04-15 19:48:57 +00:00
Dan Gohman
a2ec3156eb
Add a folding table entry for MOV8rr_NOREX.
...
llvm-svn: 69203
2009-04-15 19:48:28 +00:00
Dan Gohman
2b965abea4
Fix X86MachineFunctionInfo's doxygen comment.
...
llvm-svn: 69127
2009-04-15 01:20:18 +00:00
Dan Gohman
56227ee26e
Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with
...
the local register allocator.
llvm-svn: 69115
2009-04-15 00:10:16 +00:00
Dan Gohman
a1fe2a3741
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when
...
either the source or destination is a physical h register.
This fixes sqlite3 with the post-RA scheduler enabled.
llvm-svn: 69111
2009-04-15 00:04:23 +00:00
Dan Gohman
1e76e65007
GR8_NOREX can contain the H registers, since they don't require
...
REX prefixes.
llvm-svn: 69108
2009-04-15 00:00:48 +00:00
Dan Gohman
365c457893
For the h-register addressing-mode trick, use the correct value for
...
any non-address uses of the address value. This fixes 186.crafty.
llvm-svn: 69094
2009-04-14 22:45:05 +00:00
Evan Cheng
b64f2c1b08
Some of GR8_NOREX registers are only available in 64-bit mode.
...
llvm-svn: 69049
2009-04-14 16:57:43 +00:00
Sanjiv Gupta
b03b007054
Handle aggregate type arguments to direct and indirect calls.
...
llvm-svn: 69022
2009-04-14 02:49:52 +00:00
Dan Gohman
8393d29bc8
Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
...
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
llvm-svn: 68986
2009-04-13 21:06:25 +00:00
Devang Patel
ad7f61c279
Reapply 68847.
...
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.
llvm-svn: 68964
2009-04-13 17:02:03 +00:00
Dan Gohman
be7227005f
Implement x86 h-register extract support.
...
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 16:09:41 +00:00
Dan Gohman
f117bbdbcd
Remove x86's special-case handling for ISD::TRUNCATE and
...
ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.
llvm-svn: 68959
2009-04-13 15:29:31 +00:00
Dan Gohman
6e6f9e3a4f
Fix copy+pastos in comments.
...
llvm-svn: 68958
2009-04-13 15:28:29 +00:00
Dan Gohman
ac6a439313
List the l registers before h registers, for consistency.
...
llvm-svn: 68954
2009-04-13 15:18:42 +00:00
Dan Gohman
e1db797df3
Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.
...
llvm-svn: 68951
2009-04-13 15:14:03 +00:00
Dan Gohman
a68d99c707
Add a comment about MOVSX64rr8.
...
llvm-svn: 68950
2009-04-13 15:13:28 +00:00
Dan Gohman
65bafadd2b
Fix another hard-coded constant to use X86AddrNumOperands.
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This unbreaks the JIT on x86-64.
llvm-svn: 68948
2009-04-13 15:04:25 +00:00
Rafael Espindola
72347bffce
X86-64 TLS support for local exec and initial exec.
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llvm-svn: 68947
2009-04-13 13:02:49 +00:00
Sanjiv Gupta
04a7716d62
While passing arg of types larger than char only one byte at lower end was getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256.
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llvm-svn: 68946
2009-04-13 09:38:38 +00:00
Chris Lattner
c1bfdc9bb2
Add a new "available_externally" linkage type. This is intended
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to support C99 inline, GNU extern inline, etc. Related bugzilla's
include PR3517, PR3100, & PR2933. Nothing uses this yet, but it
appears to work.
llvm-svn: 68940
2009-04-13 05:44:34 +00:00
Rafael Espindola
ad8137187c
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
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only if symbolic addresses are RIP relatives.
llvm-svn: 68924
2009-04-12 23:00:38 +00:00
Rafael Espindola
2b0a01bda9
refactor some code into X86DAGToDAGISel::MatchWrapper
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llvm-svn: 68915
2009-04-12 21:55:03 +00:00
Chris Lattner
6d6cf3ff4a
fix a cross-block fastisel crash handling overflow intrinsics.
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See comment for details. This fixes rdar://6772169
llvm-svn: 68890
2009-04-12 07:51:14 +00:00
Chris Lattner
6a9e77c980
simplify code by using IntrinsicInst.
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llvm-svn: 68887
2009-04-12 07:36:01 +00:00
Chris Lattner
da05d37aa1
Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
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hasImplicitDefOfPhysReg methods. Use them to remove a
look in X86 fast isel.
llvm-svn: 68886
2009-04-12 07:26:51 +00:00
Dan Gohman
ac11c8d30f
Revert r68847. It breaks the build on non-Darwin targets, with this message
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from the assembler:
Error: unknown pseudo-op: `.debug_inlined'
llvm-svn: 68863
2009-04-11 15:57:04 +00:00
Devang Patel
6f907173e0
Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
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Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.
llvm-svn: 68847
2009-04-11 00:16:47 +00:00
Sanjiv Gupta
6962a75641
Added code to handle spilling and reloading of FSRs.
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llvm-svn: 68783
2009-04-10 15:10:14 +00:00
Rafael Espindola
88986ef511
Don't fold a load if the other operand is a TLS address.
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With this we generate
movl %gs:0, %eax
leal i@NTPOFF(%eax), %eax
instead of
movl $i@NTPOFF, %eax
addl %gs:0, %eax
llvm-svn: 68778
2009-04-10 10:09:34 +00:00
Chris Lattner
26aee059ba
a few fixes to "addrspace(256) is reference offset of GS segment register".
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It turns out that there are still several problems with this, will file a bugzilla.
llvm-svn: 68749
2009-04-10 00:16:23 +00:00
Bill Wendling
5d9538852f
Pass in the std::string parameter instead of returning it by value.
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llvm-svn: 68747
2009-04-10 00:12:49 +00:00
Dan Gohman
8121b3f88d
Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
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code that uses it by using SelectionDAG::getVTList instead.
llvm-svn: 68744
2009-04-09 23:54:40 +00:00
Owen Anderson
bd340ca405
Give register alias checking the hash table treatment too.
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llvm-svn: 68730
2009-04-09 22:19:30 +00:00
Bob Wilson
c53238dff1
Fix pr3954. The register scavenger asserts for inline assembly with
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register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Sanjiv Gupta
14c26ced49
The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand.
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llvm-svn: 68713
2009-04-09 17:06:24 +00:00
Sanjiv Gupta
daa922501d
Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value.
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llvm-svn: 68705
2009-04-09 10:29:32 +00:00
Chris Lattner
e0d0edaf3f
Fix code size computation on x86-64, patch by Zoltan Varga!
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llvm-svn: 68690
2009-04-09 06:10:51 +00:00
Sanjiv Gupta
3baf157321
r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.
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llvm-svn: 68671
2009-04-09 04:03:43 +00:00
Owen Anderson
d4ce32ccae
Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
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llvm-svn: 68669
2009-04-09 03:50:16 +00:00
Dan Gohman
6cb1387261
Fix grammaros in comments.
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llvm-svn: 68666
2009-04-09 02:06:09 +00:00
Rafael Espindola
7eb72dc5f2
Re-apply 68552.
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Tested by bootstrapping llvm-gcc and using that to build llvm.
llvm-svn: 68645
2009-04-08 21:14:34 +00:00
Bob Wilson
a4abfb962e
Fix PR3795: Apply Dan's suggested fix for
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ARMTargetLowering::isLegalAddressingMode.
llvm-svn: 68619
2009-04-08 17:55:28 +00:00
Rafael Espindola
d4563305fd
Avoid a hard coded constant.
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llvm-svn: 68603
2009-04-08 08:09:33 +00:00
Sanjiv Gupta
8830b56cba
Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.
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llvm-svn: 68602
2009-04-08 06:24:04 +00:00
Sanjiv Gupta
bbb78a0034
Handle indirect function calls.
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Every function has the address of its frame in the beginning of code section.
The frame address is retrieved and used to pass arguments.
llvm-svn: 68597
2009-04-08 05:38:48 +00:00
Dan Gohman
c9ce27d6b7
Implement support for using modeling implicit-zero-extension on x86-64
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with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 00:15:30 +00:00
Bill Wendling
6e702cf68c
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
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builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
llvm-svn: 68560
2009-04-07 22:35:25 +00:00
Rafael Espindola
0324937229
Reduce code duplication on the TLS implementation.
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This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
llvm-svn: 68552
2009-04-07 21:37:46 +00:00
Jim Grosbach
e2b20a3526
PR2985 / <rdar://problem/6584986>
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When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
Bob Wilson
39c7bec188
Handle 'a' modifier in ARM inline assembly.
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Patch by Richard Pennington.
llvm-svn: 68464
2009-04-06 21:46:51 +00:00
Sanjiv Gupta
14d86f7755
Map stack based frameindices for spills to zero based indices that can be accessed based on an external symbol defining the location of temporary data for a function. For example: we have spill slots addressed as foo.tmp + 0, foo.tmp + 1 etc.
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llvm-svn: 68442
2009-04-06 10:54:50 +00:00
Bob Wilson
ff3674d456
Wrap some lines to fix indentation problems.
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llvm-svn: 68405
2009-04-03 21:08:42 +00:00
Bob Wilson
a3dcb2e72d
Fix some comments.
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llvm-svn: 68404
2009-04-03 20:53:25 +00:00
Oscar Fuentes
12e0c78bd9
CMake: removed IA64AsmPrinter.cpp from lib/Target/IA64/CMakeLists.txt
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llvm-svn: 68384
2009-04-03 12:11:43 +00:00
Anton Korobeynikov
9dc98b6a85
Separate MIPS asmprinter
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llvm-svn: 68383
2009-04-03 10:41:41 +00:00
Anton Korobeynikov
ae60cc4eba
Fix target library name
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llvm-svn: 68382
2009-04-03 10:41:17 +00:00
Anton Korobeynikov
dbc41d2422
Fix comment
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llvm-svn: 68381
2009-04-03 10:41:00 +00:00
Anton Korobeynikov
b2c736f296
Move IA64 asmprinter to separate library
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llvm-svn: 68380
2009-04-03 10:38:51 +00:00
Mon P Wang
f829fb5cab
Added a x86 dag combine to increase the chances to use a
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movq for v2i64 on x86-32.
llvm-svn: 68368
2009-04-03 02:43:30 +00:00
Sanjiv Gupta
7ec088a3de
Fixed build warnings.
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llvm-svn: 68333
2009-04-02 18:33:12 +00:00
Sanjiv Gupta
01fb90085c
To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize.
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llvm-svn: 68329
2009-04-02 18:03:10 +00:00
Sanjiv Gupta
1555a0a503
Params are not being generated as static globals now. The caller passes them onto the callee's stack directly and the callee loads the argvals from its own stack. Clang generated frameindexes validatd by recalculating the stack as if all frameindexes represent 1-byte slots.
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llvm-svn: 68327
2009-04-02 17:42:00 +00:00
Chris Lattner
f1719bf7b5
silence warning in release-asserts build.
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llvm-svn: 68253
2009-04-01 22:14:45 +00:00
Dan Gohman
770f4158e5
Use CHAR_BIT instead of hard-coding 8 in several places where it
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is appropriate. This helps visually differentiate host-oriented
calculations from target-oriented calculations.
llvm-svn: 68227
2009-04-01 18:45:54 +00:00
Dan Gohman
818a08f22e
Use LLVM type names instead of C type names in comments, to be
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less ambiguous and less C-specific.
llvm-svn: 68219
2009-04-01 18:10:16 +00:00
Bob Wilson
5b42ebe6a9
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
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assembly.
llvm-svn: 68218
2009-04-01 17:58:54 +00:00
Evan Cheng
44fdb5d570
i128 shift libcalls are not available on x86.
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llvm-svn: 68133
2009-03-31 19:38:51 +00:00
Dan Gohman
86e4d0130c
Reapply 68073, with fixes. EH Landing-pad basic blocks are not
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entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.
llvm-svn: 68129
2009-03-31 18:39:13 +00:00
Rafael Espindola
3d866ac20c
remove unused arguments.
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llvm-svn: 68109
2009-03-31 16:16:57 +00:00
Bill Wendling
28fad6fcc1
Really temporarily revert r68073.
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llvm-svn: 68100
2009-03-31 08:42:40 +00:00
Bill Wendling
1c40c8c242
Oy! When reverting r68073, I added in experimental code. Sorry...
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llvm-svn: 68099
2009-03-31 08:41:31 +00:00
Bill Wendling
4706abded2
Revert r68073. It's causing a failure in the Apple-style builds.
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llvm-svn: 68092
2009-03-31 08:26:26 +00:00
Evan Cheng
5c02e62620
X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead.
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This is not yet enabled.
llvm-svn: 68082
2009-03-31 01:13:53 +00:00
Dan Gohman
29694088d3
Except in asm-verbose mode, avoid printing labels for blocks that are
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only reachable via fall-through edges. This dramatically reduces the
number of labels printed, and thus also the number of labels the
assembler must parse and remember.
llvm-svn: 68073
2009-03-30 22:55:17 +00:00
Evan Cheng
3e30bcbd69
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
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llvm-svn: 68066
2009-03-30 21:36:47 +00:00
Bob Wilson
d59a64d436
Fix comment to match function name.
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llvm-svn: 68050
2009-03-30 18:49:37 +00:00
Anton Korobeynikov
880f98920c
Fix thinko: put stuff with both global and local relocations into data.rel{.ro}, not .local
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llvm-svn: 68036
2009-03-30 17:37:43 +00:00
Anton Korobeynikov
0404baca28
Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
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llvm-svn: 68032
2009-03-30 15:27:43 +00:00
Anton Korobeynikov
2ea565a37b
Add data.rel stuff
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llvm-svn: 68031
2009-03-30 15:27:03 +00:00
Anton Korobeynikov
424bf7a0b5
IA64 is as weird as Alpha wrt r/o relocs :)
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llvm-svn: 68007
2009-03-29 17:14:35 +00:00
Anton Korobeynikov
55097e65d6
Alpha always requires global relocations to be r/w regardless of PIC.
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llvm-svn: 68006
2009-03-29 17:14:14 +00:00
Anton Korobeynikov
ec131d94ff
Honour relocation behaviour stuff for ro objects
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llvm-svn: 68005
2009-03-29 17:13:49 +00:00
Chris Lattner
9b435e06e4
add a note
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llvm-svn: 67953
2009-03-28 19:26:55 +00:00
Rafael Espindola
34f59009d1
Use array_lengthof
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llvm-svn: 67950
2009-03-28 19:02:18 +00:00
Rafael Espindola
37522e768a
Have only one definition of X86AddrNumOperands.
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llvm-svn: 67949
2009-03-28 18:55:31 +00:00
Rafael Espindola
884992a7e9
Make code a bit less brittle by no hardcoding the number
...
of operands in an address in so many places.
llvm-svn: 67945
2009-03-28 17:03:24 +00:00
Evan Cheng
a15fdaa292
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
...
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
llvm-svn: 67917
2009-03-28 05:57:29 +00:00
Jim Grosbach
93b0fc3ba8
remove trailing whitespace
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llvm-svn: 67874
2009-03-27 23:06:27 +00:00