Igor Breger
31205fdf6a
AVX512:Implemented encoding for the vmovq.s instruction.
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Differential Revision: http://reviews.llvm.org/D14810
llvm-svn: 254248
2015-11-29 07:41:26 +00:00
Alexey Bataev
3304453808
Alternative to long nops for X86 CPUs, by Andrey Turetsky
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Make X86AsmBackend generate smarter nops instead of a bunch of 0x90 for code alignment for CPUs which don't support long nop instructions.
Differential Revision: http://reviews.llvm.org/D14178
llvm-svn: 253557
2015-11-19 11:44:35 +00:00
Igor Breger
0a68600909
AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions.
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Differential Revision: http://reviews.llvm.org/D14702
llvm-svn: 253548
2015-11-19 08:26:56 +00:00
Igor Breger
fb07c48ef1
AVX512: Implemented encoding for the vmovss.s and vmovsd.s instructions.
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Differential Revision: http://reviews.llvm.org/D14771
llvm-svn: 253547
2015-11-19 07:58:33 +00:00
Igor Breger
8a3c708d1f
AVX512: Implemented encoding for the follow instructions.
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vmovapd.s, vmovaps.s, vmovdqa32.s, vmovdqa64.s, vmovdqu16.s, vmovdqu32.s, vmovdqu64.s, vmovdqu8.s, vmovupd.s, vmovups.s
Differential Revision: http://reviews.llvm.org/D14768
llvm-svn: 253546
2015-11-19 07:43:43 +00:00
Igor Breger
d09bcb79bc
AVX512: Implemented encoding for vpextrw.s instruction.
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Differential Revision: http://reviews.llvm.org/D14766
llvm-svn: 253447
2015-11-18 08:46:16 +00:00
Igor Breger
06ae954df6
AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions.
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Differential Revision: http://reviews.llvm.org/D14322
llvm-svn: 253185
2015-11-16 07:22:00 +00:00
Igor Breger
02e6595c76
Revert r253160.
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It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.
llvm-svn: 253163
2015-11-15 12:19:11 +00:00
Igor Breger
3ec0d86d6a
AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions.
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Differential Revision: http://reviews.llvm.org/D14322
llvm-svn: 253160
2015-11-15 07:23:13 +00:00
Michael Zuckerman
b36f5b984e
[x86] translating "fp" (floating point) instructions from {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp}
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LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr.
GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions.
Differential Revision: http://reviews.llvm.org/D14217
llvm-svn: 252908
2015-11-12 16:58:51 +00:00
Douglas Katzman
f853537965
Visibly fail if attempting to encode register AH,BH,CH,DH in a REX-prefixed instruction.
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Differential Revision: http://reviews.llvm.org/D13316
Fixes PR25003
llvm-svn: 252743
2015-11-11 15:51:16 +00:00
Igor Breger
bfb07ae48a
AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD instructions.
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Differential Revision: http://reviews.llvm.org/D14492
llvm-svn: 252592
2015-11-10 07:09:07 +00:00
Asaf Badouh
f3f551dd7e
revert rev. 252153 due to build failure on ubuntu
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[X86][AVX512] add comi with Sae
llvm-svn: 252154
2015-11-05 08:55:54 +00:00
Asaf Badouh
c9c8bfa4c4
[X86][AVX512] add comi with Sae
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add builtin_ia32_vcomisd and builtin_ia32_vcomisd
Differential Revision: http://reviews.llvm.org/D14331
llvm-svn: 252153
2015-11-05 08:45:06 +00:00
Asaf Badouh
e9eadcdf13
[X86][AVX512] small bugfix in VPBROADCASTM
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VPBROADCASTMW2D and VPBROADCASTMB2Q
Differential Revision: http://reviews.llvm.org/D14335
llvm-svn: 252151
2015-11-05 08:08:21 +00:00
Rafael Espindola
1d7efb8a20
Fix pr24832.
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It is pretty simple now that the yak is shaved.
llvm-svn: 252105
2015-11-05 00:10:08 +00:00
Igor Breger
207c14b67f
AVX512: add encoding tests for vmovq/d instructions.
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llvm-svn: 251903
2015-11-03 07:30:17 +00:00
Igor Breger
dd070c17bb
AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and VBROADCASTF32x2 instructions.
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Differential Revision: http://reviews.llvm.org/D14216
llvm-svn: 251781
2015-11-02 07:39:36 +00:00
Asaf Badouh
2110df5fda
[X86][AVX512] [X86][AVX512] add convert float to half
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convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem).
Differential Revision: http://reviews.llvm.org/D14113
llvm-svn: 251409
2015-10-27 15:37:17 +00:00
David Majnemer
0e608b0bdb
[MC] Add support for GNU as-compatible binary operator precedence
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GNU as and Darwin give the various binary operators different
precedence. LLVM's MC supported the Darwin semantics but not the GNU
semantics.
This fixes PR25311.
llvm-svn: 251271
2015-10-26 03:15:34 +00:00
Asaf Badouh
99f2354837
[X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versions
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Differential Revision: http://reviews.llvm.org/D13945
llvm-svn: 251018
2015-10-22 14:01:16 +00:00
Craig Topper
dcce633156
[X86] Add AMD mwaitx, monitorx, and clzero instructions to the assembly parser and disassembler.
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llvm-svn: 250911
2015-10-21 17:26:45 +00:00
Igor Breger
c385abd09d
AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.
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Differential Revision: http://reviews.llvm.org/D13884
llvm-svn: 250819
2015-10-20 11:56:42 +00:00
Asaf Badouh
381b11d5f2
[X86][AVX512DQ] add scalar fpclass
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Differential Revision: http://reviews.llvm.org/D13769
llvm-svn: 250650
2015-10-18 11:04:38 +00:00
Igor Breger
6e29702ee8
AVX512: Implemented encoding and intrinsics for vpternlogd/q.
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Differential Revision: http://reviews.llvm.org/D13768
llvm-svn: 250396
2015-10-15 12:33:24 +00:00
Craig Topper
18c728de25
[X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser will check the size.
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llvm-svn: 250012
2015-10-12 04:17:55 +00:00
Craig Topper
7a2aafba5d
[X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior.
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This also fixes a bug where negative immediates below -128 were not being reported as errors.
llvm-svn: 249989
2015-10-11 18:27:24 +00:00
Igor Breger
63cd1bda1b
AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation.
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This instructions doesn't have intrincis.
Added tests for lowering and encoding.
Differential Revision: http://reviews.llvm.org/D12317
llvm-svn: 249688
2015-10-08 12:55:01 +00:00
Igor Breger
495e2a8625
AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented.
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Add encoding tests.
Differential Revision: http://reviews.llvm.org/D13471
llvm-svn: 249521
2015-10-07 06:31:18 +00:00
Igor Breger
38dd6d8710
AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12690
llvm-svn: 249261
2015-10-04 07:20:41 +00:00
Asaf Badouh
8011b4b495
[X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP
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Differential Revision: http://reviews.llvm.org/D12524
llvm-svn: 248147
2015-09-21 10:23:53 +00:00
Igor Breger
a833017e0d
AVX512: Implemented encoding and intrinsics for vcmpss/sd.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12593
llvm-svn: 248121
2015-09-20 15:15:10 +00:00
Asaf Badouh
4ce11a0a36
[X86][AVX512] extend support in Scalar conversion
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add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics
Differential Revision: http://reviews.llvm.org/D12665
llvm-svn: 248117
2015-09-20 14:31:19 +00:00
Igor Breger
6c78cd17ac
AVX512: vsqrtss/sd encoding and intrinsics implementation.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12102
llvm-svn: 248116
2015-09-20 09:13:41 +00:00
Asaf Badouh
981ab82bef
[X86][AVX512DQ] Add fpclass instruction
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Differential Revision: http://reviews.llvm.org/D12931
llvm-svn: 248115
2015-09-20 08:46:07 +00:00
Igor Breger
43e0d98a01
AVX512: Implement instructions encoding, lowering and intrinsics
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vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.
Differential Revision: http://reviews.llvm.org/D11893
llvm-svn: 248111
2015-09-20 06:52:42 +00:00
Igor Breger
eeecfc6724
AVX512: Implemented encoding and intrinsics for
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vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11802
llvm-svn: 247276
2015-09-10 12:54:54 +00:00
Renato Golin
32a92f6d16
Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."
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This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.
llvm-svn: 247177
2015-09-09 19:44:40 +00:00
Igor Breger
1a3ef530c1
AVX512: Implemented encoding and intrinsics for
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vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11802
llvm-svn: 247149
2015-09-09 14:35:09 +00:00
Igor Breger
2caf00654a
AVX512: kunpck encoding implementation
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Added tests for encoding.
Differential Revision: http://reviews.llvm.org/D12061
llvm-svn: 247010
2015-09-08 13:10:00 +00:00
Igor Breger
63fab329a2
AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflictq, vpconflictd
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11931
llvm-svn: 246750
2015-09-03 09:05:31 +00:00
Asaf Badouh
70ff5c87a7
[X86][AVX512VLBW] add support in byte shift and SAD
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add byte shift left/right
add SAD - compute sum of absolute differences
Differential Revision: http://reviews.llvm.org/D12479
llvm-svn: 246654
2015-09-02 14:21:54 +00:00
Igor Breger
8e7d569bab
AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S instructions
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11593
llvm-svn: 246642
2015-09-02 11:18:55 +00:00
Igor Breger
dc46fb3351
AVX512: Implemented encoding and intrinsics for vshufps/d.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11709
llvm-svn: 246640
2015-09-02 10:50:58 +00:00
Igor Breger
e7da3698f2
AVX512: ktest implemantation
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Added tests for encoding.
Differential Revision: http://reviews.llvm.org/D11979
llvm-svn: 246439
2015-08-31 13:30:19 +00:00
Igor Breger
2ff3c16585
AVX512: Implemented encoding and intrinsics for vdbpsadbw
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12491
llvm-svn: 246436
2015-08-31 13:09:30 +00:00
Igor Breger
d931ce02d4
AVX512: kadd implementation
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Added tests for encoding.
Differential Revision: http://reviews.llvm.org/D11973
llvm-svn: 246432
2015-08-31 11:50:23 +00:00
Igor Breger
0b3d48f3ef
AVX512: Add encoding tests for vscatter instructions
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Differential Revision: http://reviews.llvm.org/D11941
llvm-svn: 246431
2015-08-31 11:33:50 +00:00
Igor Breger
c6e71f91ab
AVX512: Implemented encoding and intrinsics for vpalignr
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12270
llvm-svn: 246428
2015-08-31 11:14:02 +00:00
Michael Zuckerman
ae040817a7
[X86] Add support for mmword memory operand size for Intel-syntax x86 assembly
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Differential Revision: http://reviews.llvm.org/D12151
llvm-svn: 245835
2015-08-24 10:26:54 +00:00