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Commit Graph

5680 Commits

Author SHA1 Message Date
Dale Johannesen
312df3aa6d Make earlyclobber stuff work when virtual regs
have previously been assigned conflicting physreg.

llvm-svn: 56364
2008-09-19 18:52:31 +00:00
Evan Cheng
14493ffe78 Re-materalized definition instructions may be dead. Whack them.
llvm-svn: 56352
2008-09-19 17:38:47 +00:00
Dale Johannesen
214ddc92d0 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk.  Logic moved into RA.
Per review feedback.

llvm-svn: 56326
2008-09-19 01:02:35 +00:00
Evan Cheng
bcd694a1b4 Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
llvm-svn: 56314
2008-09-18 22:38:47 +00:00
Dan Gohman
9dc56fbe40 Don't consider instructions with implicit physical register
defs to be necessarily live.

llvm-svn: 56310
2008-09-18 18:22:32 +00:00
Dan Gohman
b7c5b0f44b Add a new "fast" scheduler. This is currently basically just a
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.

This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.

llvm-svn: 56307
2008-09-18 16:26:26 +00:00
Dale Johannesen
99091ed94f Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals.
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
Dan Gohman
4bef47e8c3 Don't worry about clobbering physical register defs that aren't used.
llvm-svn: 56281
2008-09-17 15:25:49 +00:00
Dan Gohman
d0c6cb65e8 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel.

llvm-svn: 56268
2008-09-17 00:43:24 +00:00
Evan Cheng
6cfbecd1fa When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
llvm-svn: 56258
2008-09-16 23:12:11 +00:00
Dan Gohman
9cbb3f591a Change SelectionDAG::getConstantPool to always set the alignment of the
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!

llvm-svn: 56253
2008-09-16 22:05:41 +00:00
Bill Wendling
932818c75a Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Dan Gohman
6da3227304 Include the alignment value when displaying ConstantPoolSDNodes.
llvm-svn: 56250
2008-09-16 21:18:22 +00:00
Bill Wendling
1a240c8033 - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman
f89b35c261 Fix these comments to reflect current reality. Surprisingly,
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.

llvm-svn: 56248
2008-09-16 20:45:53 +00:00
Dan Gohman
37457ca74b Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
are not enabled. Instead just omit the tail call flag when calls are
created.

llvm-svn: 56235
2008-09-16 01:42:28 +00:00
Owen Anderson
553caa6ed4 Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.

llvm-svn: 56231
2008-09-15 22:00:38 +00:00
Dan Gohman
f38d63884f Re-enable SelectionDAG CSE for calls. It matters in the case of
libcalls, as in this testcase on ARM.

llvm-svn: 56226
2008-09-15 19:46:03 +00:00
Evan Cheng
db1693cb14 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
Dale Johannesen
57fc1bdfdc adjust last patch per review feedback
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
Dan Gohman
fa32c7c6d9 Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Dan Gohman
3450a8252f Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183
2008-09-13 01:54:27 +00:00
Evan Cheng
07046dae41 On some targets, non-move instructions can become move instructions because of coalescing. e.g.
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165
2008-09-12 18:13:14 +00:00
Dan Gohman
082879cfde Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162
2008-09-12 18:08:03 +00:00
Dale Johannesen
6395da3510 Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161
2008-09-12 17:49:03 +00:00
Dan Gohman
89660301e3 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Dale Johannesen
fbc17046ff The sequence for ppcf128 compares was not IEEE
safe in the presence of NaNs.

llvm-svn: 56136
2008-09-12 00:30:56 +00:00
Evan Cheng
5c7e3783ef Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118
2008-09-11 20:07:10 +00:00
Evan Cheng
99be914c9a Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
llvm-svn: 56112
2008-09-11 18:40:32 +00:00
Evan Cheng
9de997d5de Fix a 80 column violation.
llvm-svn: 56097
2008-09-11 05:58:06 +00:00
Evan Cheng
b879f93ba5 Propagate subreg index when promoting a load to a copy.
llvm-svn: 56085
2008-09-11 01:02:12 +00:00
Dan Gohman
ad5824104b FastISel support for i1 PHI nodes.
llvm-svn: 56069
2008-09-10 21:01:31 +00:00
Dan Gohman
5a6134a875 FastISel support for i1 constants.
llvm-svn: 56068
2008-09-10 21:01:08 +00:00
Owen Anderson
6bcc01b3eb Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it. This
was exposed by fast isel's handling of shifts on X86-64.  With this, FreeBench/pcompress2 passes on X86-64 in fast isel.

llvm-svn: 56067
2008-09-10 20:41:13 +00:00
Dan Gohman
3ccdde5eef Add X86FastISel support for static allocas, and refences
to static allocas. As part of this change, refactor the
address mode code for laods and stores.

llvm-svn: 56066
2008-09-10 20:11:02 +00:00
Evan Cheng
474ba35954 Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machine operands.
llvm-svn: 56065
2008-09-10 20:08:45 +00:00
Dan Gohman
5211f1f5fc Add a break statement that I accidentally deleted when
I shuffled the fast-isel command-line options around. This fixes
a bunch of fast-isel failures.

llvm-svn: 56057
2008-09-10 15:52:34 +00:00
Bill Wendling
c7c5d73866 Remove unnecessary bit-wise AND from the limited precision work.
llvm-svn: 56049
2008-09-10 06:26:10 +00:00
Daniel Dunbar
df44fb835c Fix 80 col violation.
llvm-svn: 56048
2008-09-10 04:16:29 +00:00
Evan Cheng
1ac90281be Fix typo.
llvm-svn: 56037
2008-09-10 00:30:50 +00:00
Bill Wendling
4dc9d148b5 Check that both operands are f32 before attempting to lower.
llvm-svn: 56036
2008-09-10 00:24:59 +00:00
Bill Wendling
aa39e64468 Implement "visitPow". This is mainly used to see if we have a pow() call of this
form:

          powf(10.0f, x);

If this is the case, and also we want limited precision floating-point
calculations, then lower to do the limited-precision stuff.

llvm-svn: 56035
2008-09-10 00:20:20 +00:00
Evan Cheng
150ee094e2 A few more places where FPOW is being ignored.
llvm-svn: 56032
2008-09-09 23:35:53 +00:00
Dan Gohman
5b55c46044 Change -fast-isel-no-abort to -fast-isel-abort, which now defaults
to being off by default. Also, add assertion checks to check that
the various fast-isel-related command-line options are only used
when -fast-isel itself is enabled.

llvm-svn: 56029
2008-09-09 23:05:00 +00:00
Evan Cheng
ba11945234 Legalizer was missing code that expand fpow to a libcall.
llvm-svn: 56028
2008-09-09 23:02:14 +00:00
Bill Wendling
5d6d774240 Adding 6-, 12-, and 18-bit limited-precision floating-point support for exp2
function.

llvm-svn: 56025
2008-09-09 22:39:21 +00:00
Dale Johannesen
ba2bbe0c55 Move the uglier parts of deciding not to emit a
UsedDirective for some symbols in llvm.used into
Darwin-specific code.  I've decided LessPrivateGlobal
is potentially a useful abstraction and left it in
the target-independent area, with improved comment.

llvm-svn: 56024
2008-09-09 22:29:13 +00:00
Bill Wendling
103d08d4ce Add support for 6-, 12-, and 18-bit limited precision calculations of exp for
floating-point numbers.

llvm-svn: 56023
2008-09-09 22:13:54 +00:00
Dan Gohman
2799e1dc63 Add a new option, -fast-isel-verbose, that can be used with
-fast-isel-no-abort to get a dump of all unhandled instructions,
without an abort.

llvm-svn: 56021
2008-09-09 22:06:46 +00:00