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Commit Graph

181775 Commits

Author SHA1 Message Date
Heejin Ahn
db7b3ceca1 [WebAssembly] Print error message for llvm.clear_cache intrinsic
Summary:
Wasm does not currently support `llvm.clear_cache` intrinsic, and this
prints a proper error message instead of segfault.

Reviewers: dschuff, sbc100, sunfish

Subscribers: jgravelle-google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64322

llvm-svn: 365731
2019-07-11 05:55:47 +00:00
Huihui Zhang
fe28d8b7b6 [InstCombine][NFCI] Add test coverage to onehot_merge.ll
Prep work for upcoming patch D64275.

llvm-svn: 365729
2019-07-11 04:56:37 +00:00
Chen Zheng
90e55c89d2 [SCEV] teach SCEV symbolical execution about overflow intrinsics folding.
Differential Revision: https://reviews.llvm.org/D64422

llvm-svn: 365726
2019-07-11 02:18:22 +00:00
Johannes Doerfert
50ae2e4d25 Replace three "strip & accumulate" implementations with a single one
This patch replaces the three almost identical "strip & accumulate"
implementations for constant pointer offsets with a single one,
combining the respective functionalities. The old interfaces are kept
for now.

Differential Revision: https://reviews.llvm.org/D64468

llvm-svn: 365723
2019-07-11 01:14:48 +00:00
Johannes Doerfert
1f3d696f06 [NFC] Adjust "invalid.ll.bc" tests to check for AttrKind #255 not #63
We are about to add enum attributes with AttrKind numbers >= 63. This
means we cannot use AttrKind #63 to test for an invalid attribute number
in the RAW format anymore. This patch changes the number of an invalid
attribute to #255. There is no change to the character of the tests.

Differential Revision: https://reviews.llvm.org/D64531

llvm-svn: 365722
2019-07-11 01:14:30 +00:00
Craig Topper
24807ec799 [X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.
We use the functions that convert to three address to do the
conversion, but changing an 8 or 16 bit will cause it to create
a virtual register. This can't be done after register allocation
where this pass runs.

I've switched the pass completely to a white list of instructions
that can be converted to LEA instead of a blacklist that was
incorrect. This will avoid surprises if we enhance the three
address conversion function to include additional instructions
in the future.

Fixes PR42565.

llvm-svn: 365720
2019-07-11 01:01:39 +00:00
Stanislav Mekhanoshin
f44b2e953d [AMDGPU] gfx908 atomic fadd and atomic pk_fadd
Differential Revision: https://reviews.llvm.org/D64435

llvm-svn: 365717
2019-07-11 00:10:17 +00:00
Stanislav Mekhanoshin
38bf3a3a26 [AMDGPU] gfx908 dot instruction support
Differential Revision: https://reviews.llvm.org/D64431

llvm-svn: 365715
2019-07-11 00:00:27 +00:00
Jordan Rupprecht
52ffd53e37 Revert [llvm-objcopy] Allow strip symtab from executables and DSOs
This reverts r365193 (git commit 194f16b3548bcb23a7f0fd638778ed72edd18d37)

This patch doesn't work with binaries built w/ `--emit-relocs`, e.g.

```
$ echo 'int main() { return 0; }' | clang -Wl,--emit-relocs -x c - -o foo && llvm-objcopy --strip-unneeded foo
llvm-objcopy: error: 'foo': not stripping symbol '__gmon_start__' because it is named in a relocation
```

llvm-svn: 365712
2019-07-10 23:32:44 +00:00
Sanjay Patel
f458c125da [SDAG] commute setcc operands to match a subtract
If we have:

R = sub X, Y
P = cmp Y, X

...then flipping the operands in the compare instruction can allow using a subtract that sets compare flags.

Motivated by diffs in D58875 - not sure if this changes anything there,
but this seems like a good thing independent of that.

There's a more involved version of this transform already in IR (in instcombine
although that seems misplaced to me) - see "swapMayExposeCSEOpportunities()".

Differential Revision: https://reviews.llvm.org/D63958

llvm-svn: 365711
2019-07-10 23:23:54 +00:00
Vitaly Buka
1998d38e13 Add IsBytewiseValue unit test
Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63966

llvm-svn: 365710
2019-07-10 22:56:15 +00:00
Vitaly Buka
4d595bf761 NFC: Pass DataLayout into isBytewiseValue
Summary:
We will need to handle IntToPtr which I will submit in a separate patch as it's
not going to be NFC.

Reviewers: eugenis, pcc

Reviewed By: eugenis

Subscribers: hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D63940

llvm-svn: 365709
2019-07-10 22:53:52 +00:00
Craig Topper
19b3b28976 [X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
Fixes similar issues to r352306.

llvm-svn: 365705
2019-07-10 22:44:32 +00:00
Craig Topper
cc286ceef5 [X86] Add a few more TBM and BLSI test cases that show the same issue that r352306 fixed for BLSR.
llvm-svn: 365704
2019-07-10 22:44:24 +00:00
Craig Topper
4288ec5f78 [X86] Add BLSR and BLSMSK to isUseDefConvertible.
Unfortunately subo formation in CGP prevents obvious ways of
testing this.

But we already have BLSI in here and the flag behavior is
well understood.

Might become more useful if we improve PR42571.

llvm-svn: 365702
2019-07-10 22:14:39 +00:00
David Tenty
b92d2801f8 [NFC]Fix IR/MC depency issue for function descriptor SDAG implementation
Summary: llvm/IR/GlobalValue.h can't be included in MC, that creates a circular dependency between MC and IR libraries. This circular dependency is causing an issue for build system that enforce layering.

Author: Xiangling_L

Reviewers: sfertile, jasonliu, hubert.reinterpretcast, gribozavr

Reviewed By: gribozavr

Subscribers: wuzish, nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64445

llvm-svn: 365701
2019-07-10 22:13:55 +00:00
Craig Topper
1c6efe0a44 [X86] Remove unused variable. NFC
llvm-svn: 365697
2019-07-10 21:01:34 +00:00
Roman Lebedev
8fd8cf17aa [NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more
llvm-svn: 365694
2019-07-10 19:58:13 +00:00
Nico Weber
95b0d08af1 Add support for building with Python 3
LLDB supports Python 3 now.

Differential Revision: https://reviews.llvm.org/D64443

Patch from Christian Biesinger <cbiesinger@google.com>!

llvm-svn: 365692
2019-07-10 19:31:25 +00:00
Amara Emerson
eecd26ab7d [AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and unknown values.
Since we have distinct types for pointers and scalars, G_INTTOPTRs can sometimes
obstruct attempts to find constant source values. These usually come about when
try to do some kind of null pointer check. Teaching getConstantVRegValWithLookThrough
about this operation allows the CBZ/CBNZ optimization to catch more cases.

This change also improves the case where we can't find a constant source at all.
Previously we would emit a cmp, cset and tbnz for that. Now we try to just emit
a cmp and conditional branch, saving an instruction.

The cumulative code size improvement of this change plus D64354 is 5.5% geomean
on arm64 CTMark -O0.

Differential Revision: https://reviews.llvm.org/D64377

llvm-svn: 365690
2019-07-10 19:21:43 +00:00
Nico Weber
6a298ee9be gn build: Merge r365687
llvm-svn: 365689
2019-07-10 19:20:17 +00:00
Nikola Prica
fd772afb31 Revert "[ELF] Loose a condition for relocation with a symbol"
This reverts commit 8507eca1647118e73435b0ce1de8a1952a021d01.

Reveting due to some suspicious failurse in santizer-x86_64-linux.

llvm-svn: 365685
2019-07-10 18:58:05 +00:00
Jessica Paquette
d177d58582 [GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromReg
Some minor cleanup.

This function in Utils does the same thing as `findMIFromReg`. It also looks
through copies, which `findMIFromReg` didn't.

Delete `findMIFromReg` and use `getOpcodeDef` instead. This only happens in
`tryOptVectorDup` right now.

Update opt-shuffle-splat to show that we can look through the copies now, too.

Differential Revision: https://reviews.llvm.org/D64520

llvm-svn: 365684
2019-07-10 18:46:56 +00:00
Jessica Paquette
16c02a7004 [GlobalISel][AArch64][NFC] Use getDefIgnoringCopies from Utils where we can
There are a few places where we walk over copies throughout
AArch64InstructionSelector.cpp. In Utils, there's a function that does exactly
this which we can use instead.

Note that the utility function works with the case where we run into a COPY
from a physical register. We've run into bugs with this a couple times, so using
it should defend us from similar future bugs.

Also update opt-fold-compare.mir to show that we still handle physical registers
properly.

Differential Revision: https://reviews.llvm.org/D64513

llvm-svn: 365683
2019-07-10 18:44:57 +00:00
David Greene
1a0528f138 Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"
This broke some PPC prefetching tests.

This reverts commit 9fdfb045ae8bb643ab0d0455dcf9ecaea3b1eb3c.

llvm-svn: 365680
2019-07-10 18:25:58 +00:00
Michael Berg
e6a923ea4b Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang.  I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it.  Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context. 

Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm

Reviewed By: arsenm

Subscribers: michele.scandale, wdng, javed.absar

Differential Revision: https://reviews.llvm.org/D64450

llvm-svn: 365679
2019-07-10 18:23:26 +00:00
David Greene
0c46c9cc2f [System Model] [TTI] Update cache and prefetch TTI interfaces
Rework the TTI cache and software prefetching APIs to prepare for the
introduction of a general system model.  Changes include:

- Marking existing interfaces const and/or override as appropriate
- Adding comments
- Adding BasicTTIImpl interfaces that delegate to a subtarget
  implementation
- Adding a default "no information" subtarget implementation

Only a handful of targets use these interfaces currently: AArch64,
Hexagon, PPC and SystemZ.  AArch64 already has a custom subtarget
implementation, so its custom TTI implementation is migrated to use
the new facilities in BasicTTIImpl to invoke its custom subtarget
implementation.  The custom TTI implementations continue to exist for
the other targets with this change.  They are not moved over to
subtarget-based implementations.

The end goal is to have the default subtarget implementation defer to
the system model defined by the target.  With this change, the default
subtarget implementation essentially returns "no information" for
these interfaces.  None of the existing users of TTI will hit that
implementation because they define their own custom TTI
implementations and won't use the BasicTTIImpl implementations.

Once system models are in place for the targets that use these
interfaces, their custom TTI implementations can be removed.

Differential Revision: https://reviews.llvm.org/D63614

llvm-svn: 365676
2019-07-10 18:07:01 +00:00
Don Hinton
c604692b58 Recommit "[CommandLine] Remove OptionCategory and SubCommand caches from the Option class."
Previously reverted in 364141 due to buildbot breakage, and fixed here
by making GeneralCategory global a ManagedStatic.

Summary:
This change processes `OptionCategory`s and `SubCommand`s as they
are seen instead of caching them in the Option class and processing
them later.  Doing so simplifies the work needed to be done by the Global
parser and significantly reduces the size of the Option class to a mere 64
bytes.

Removing  the `OptionCategory` cache saved 24 bytes, and removing
the `SubCommand` cache saved an additional 48 bytes, for a total of a
72 byte reduction.

Reviewed By: serge-sans-paille

Tags: #llvm, #clang

Differential Revision: https://reviews.llvm.org/D62105

llvm-svn: 365675
2019-07-10 17:57:05 +00:00
Simon Pilgrim
39790aedab [X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.
Determine the element/load size calculations earlier and assert that they are whole bytes in size.

llvm-svn: 365674
2019-07-10 17:49:27 +00:00
Alina Sbirlea
f6c8fb0687 [LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.
Summary:
The map kept in loop rotate is used for instruction remapping, in order
to simplify the clones of instructions. Thus, if an instruction can be
simplified, its simplified value is placed in the map, even when the
clone is added to the IR. MemorySSA in contrast needs to know about that
clone, so it can add an access for it.
To resolve this: keep a different map for MemorySSA.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63680

llvm-svn: 365672
2019-07-10 17:36:56 +00:00
Lang Hames
9e5d8e3243 [ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.
LLJITBuilder now has a setCompileFunctionCreator method which can be used to
construct a CompileFunction for the LLJIT instance being created. The motivating
use-case for this is supporting ObjectCaches, which can now be set up at
compile-function construction time. To demonstrate this an example project,
LLJITWithObjectCache, is included.

llvm-svn: 365671
2019-07-10 17:24:24 +00:00
Simon Pilgrim
bcdb2ccd11 [X86] Regenerate tests. NFCI.
Hasn't been regenerated since the update script could merge 32/64-bit checks.

llvm-svn: 365670
2019-07-10 17:22:31 +00:00
Craig Topper
7242a767b0 [X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC
llvm-svn: 365667
2019-07-10 17:11:18 +00:00
Nick Desaulniers
b4e302c2c3 [TargetLowering] support BlockAddress as "i" inline asm constraint
Summary:
This allows passing address of labels to inline assembly "i" input
constraints.

Fixes pr/42502.

Reviewers: ostannard

Reviewed By: ostannard

Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64167

llvm-svn: 365664
2019-07-10 17:08:25 +00:00
Roman Lebedev
00ddcc612b [NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests
llvm-svn: 365663
2019-07-10 16:54:13 +00:00
Peter Collingbourne
bbda128d72 MC: AArch64: Add support for pg_hi21_nc relocation specifier.
Differential Revision: https://reviews.llvm.org/D64455

llvm-svn: 365661
2019-07-10 16:36:46 +00:00
Vedant Kumar
3d60239dc7 [CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)
An alloca which can be sunk into the extraction region may have more
than one bitcast use. Move these uses along with the alloca to prevent
use-before-def.

Testing: check-llvm, stage2 build of clang

Fixes llvm.org/PR42451.

Differential Revision: https://reviews.llvm.org/D64463

llvm-svn: 365660
2019-07-10 16:32:20 +00:00
Vedant Kumar
b1705f20bc [CodeExtractor] Simplify findAllocas, NFC
Split getLifetimeMarkers out into its own method and have it return a
struct.

Differential Revision: https://reviews.llvm.org/D64467

llvm-svn: 365659
2019-07-10 16:32:16 +00:00
Matt Arsenault
ccac9b19ad GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM
llvm-svn: 365658
2019-07-10 16:31:19 +00:00
Matt Arsenault
2f9dc44acc GlobalISel: Define the full family of FP min/max instructions
llvm-svn: 365657
2019-07-10 16:31:15 +00:00
Simon Pilgrim
7f609642d0 [X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.
We've already checked that each element is the correct contributory size for VT when we inspect the elements for Undef/Zero/Load.

llvm-svn: 365656
2019-07-10 16:22:31 +00:00
Simon Pilgrim
47d668be45 [X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same size. NFCI.
This renames the type so it doesn't sound like its based off the load size - as we're moving towards supporting combining loads of different sizes.

llvm-svn: 365655
2019-07-10 16:14:26 +00:00
Matt Arsenault
e350c07050 AMDGPU: Serialize mode from MachineFunctionInfo
llvm-svn: 365653
2019-07-10 16:09:26 +00:00
Roman Lebedev
589005deed [PatternMatch] Generalize m_SpecificInt_ULT() to take ICmpInst::Predicate
As discussed in the original review, this may be useful,
so let's just do it.

llvm-svn: 365652
2019-07-10 16:07:35 +00:00
Francis Visoiu Mistrih
610ad72637 [Remarks] Add cl::Hidden to -remarks-yaml-string-table
It was showing up in a lot of unrelated tools.

llvm-svn: 365647
2019-07-10 15:46:36 +00:00
Tom Stellard
823dcc0017 docs/GithubMove.rst: Remove obsolete information
Summary:
Remove references to the multirepo and update the document to
reflect the current state of the github repository.

Reviewers: mehdi_amini, jyknight

Subscribers: jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58420

llvm-svn: 365645
2019-07-10 15:39:37 +00:00
Thomas Preud'homme
aaba964272 [FileCheck] Use bool operator to test Expected
Use bool() consistently to get boolean value of Error, Optional and
Expected types in EXPECT calls. While static_cast is used in all cases
but one, bool provides more clarity and makes more sense as a new
default.

llvm-svn: 365644
2019-07-10 15:31:19 +00:00
Roman Lebedev
799d996251 [NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b:     https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49

Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.

Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.

For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.

https://bugs.llvm.org/show_bug.cgi?id=42563

llvm-svn: 365641
2019-07-10 15:08:06 +00:00
Jay Foad
d27c559396 [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
Summary:
D59191 added support for these modifiers in the assembler and
disassembler. This patch just teaches instruction selection that it can
use them.

Reviewers: arsenm, tstellar

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64497

llvm-svn: 365640
2019-07-10 14:53:47 +00:00
David Bolvansky
4bd279e3cc [InstCombine] pow(C,x) -> exp2(log2(C)*x)
Summary:
Transform
pow(C,x) 

To
exp2(log2(C)*x) 

if C > 0, C != inf, C != NaN (and C is not power of 2, since we have some fold for such case already).

log(C) is folded by the compiler and exp2 is much faster to compute than pow.

Reviewers: spatel, efriedma, evandro

Reviewed By: evandro

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64099

llvm-svn: 365637
2019-07-10 14:43:27 +00:00