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Commit Graph

131533 Commits

Author SHA1 Message Date
Sanjoy Das
fc5838c877 [ValueTracking] Hoist some computation out of a loop; NFC
There is no need to match the comparison instruction repeatedly.

llvm-svn: 268836
2016-05-07 02:08:24 +00:00
Sanjoy Das
dff69bed0a Clean up comment; NFC
llvm-svn: 268835
2016-05-07 02:08:22 +00:00
Sanjoy Das
d8f828a34c Delete trailing whitespace; NFC
llvm-svn: 268834
2016-05-07 02:08:15 +00:00
Vitaly Buka
52cd534788 Revert r268810 becase it brakes msan bot.
16802==WARNING: MemorySanitizer: use-of-uninitialized-value
    lib/Target/ARM/ARMFrameLowering.cpp:1632

llvm-svn: 268833
2016-05-07 01:54:00 +00:00
Mehdi Amini
62c6d531b0 Refactor stripDebugInfo(Function) to handle intrinsic
This moves the code that handles stripping debug info intrinsic from
 StripDebugInfo(Module) to StripDebugInfo(Function). The latter is
already walking every instructions so it makes sense to do it at the
same time.
This makes also stripDebugInfo(Function) as an API more useful: it
is really dropping every debug info in the Function.
Finally the existing code is trigerring an assertion when the Module
is not fully materialized.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268832
2016-05-07 01:42:36 +00:00
Ahmed Bougacha
0eb872067d [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670

The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.

At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.

Also add MIR tests for the various interesting cases.

Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.

Differential Revision: http://reviews.llvm.org/D19999

llvm-svn: 268831
2016-05-07 01:11:17 +00:00
Ahmed Bougacha
67d42c1834 [X86] Register and initialize the FixupBW pass.
That lets us use it in MIR tests.

llvm-svn: 268830
2016-05-07 01:11:10 +00:00
Kostya Serebryany
8f61eefd2f [libFuzzer] modify the docs for startup/init
llvm-svn: 268824
2016-05-06 23:51:28 +00:00
Kostya Serebryany
9895cf9ee1 [libFuzzer] tweak the documentation about rss_limit
llvm-svn: 268822
2016-05-06 23:41:11 +00:00
Kostya Serebryany
6a10031791 [libFuzzer] enhance -rss_limit_mb and enable by default. Now it will print the OOM reproducer.
llvm-svn: 268821
2016-05-06 23:38:07 +00:00
Rong Xu
4773d4a40a [PGO] Use rsplit to parse value-data line in text profile file.
The value-data line is <PGOFuncName>:<Count_Value>. PGOFuncName might contain
':' for the internal linkage functions. We therefore need to use rsplit,
rather split, to extract the data from the line. This fixes the error when
merging a text profile file to an indexed profile file.

llvm-svn: 268818
2016-05-06 23:20:58 +00:00
Adrian Prantl
d59e8e3f10 Implement a safer bitcode upgrade for DISubprogram.
The bitcode upgrade I added for DISubprogram in r266446 was based on the
assumption that the CU node for the subprogram was already materialized by the
time the DISubprogram is visited. This assumption may not hold true as future
versions of LLVM may decide to write out bitcode in a different order. This
patch corrects this by introducing a versioning bit next to the distinct flag to
unambiguously differentiate the new from the old record layouts.

Note for people stabilizing LLVM out-of-tree: This patch introduces a bitcode
incompatibility with llvm trunk revisions from r266446 — this commit. (But
D19987 will ensure that it degrades gracefully).

http://reviews.llvm.org/D20004
rdar://problem/26074194

llvm-svn: 268816
2016-05-06 22:53:06 +00:00
Matthias Braun
7989fa182b DetectDeadLanes: Increase precision when detecting undef inputs
In case of COPY-like instruction we may be able to deduce that a certain
input is unused, based on the used lanes of the register defined by the
instruction.
This even works accross otherwise incompatible copies (no need to have
compatible lanemasks, completely unused operands are still completely
unused). It even makes sense to redo the analysis in this case since we
gained information for a case we previously stopped at because of the
incompatible masks.

llvm-svn: 268815
2016-05-06 22:43:50 +00:00
Matthias Braun
37e3c35a54 DetectDeadLanes: Cleanup, assert on some impossible cases.
llvm-svn: 268814
2016-05-06 22:43:46 +00:00
Zachary Turner
22c9b29e07 Drop error when trying to fallback from PDB to DWARF.
llvm-svn: 268813
2016-05-06 22:29:34 +00:00
Justin Bogner
9040306a47 cmake: Avoid continue, apparently that's new
llvm-svn: 268812
2016-05-06 22:22:25 +00:00
Simon Pilgrim
ffb35ca97a [SLPVectorizer][X86] Regenerated SEXT/ZEXT cast vectorization tests
Added 256-bit vector test as well

llvm-svn: 268811
2016-05-06 22:22:18 +00:00
Weiming Zhao
029301cce2 [ARM] Fix Scavenger assert due to underestimated stack size
(this is resubmit of r268529 with minor refactoring. r268529 was reverted
 at r268536 due a memory sanitizer failure.  I have not been able to
 reproduce that failure and I checked all the variable used in my change
 but I could not spot an issue. I did some refactoring and see if it will
 give a clearer hint)

Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.

Reviewers: rengolin

Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits

Differential Revision: http://reviews.llvm.org/D19896

llvm-svn: 268810
2016-05-06 22:20:13 +00:00
Philip Reames
28e49b3a15 Reapply 267210 with fix for PR27490
Original Commit Message
Extend load/store type canonicalization to handle unordered operations

Extend the type canonicalization logic to work for unordered atomic loads and stores.  Note that while this change itself is fairly simple and low risk, there's a reasonable chance this will expose problems in the backends by suddenly generating IR they wouldn't have seen before.  Anything of this nature will be an existing bug in the backend (you could write an atomic float load), but this will definitely change the frequency with which such cases are encountered.  If you see problems, feel free to revert this change, but please make sure you collect a test case. 

Note that the concern about lowering is now much less likely.  PR27490 proved that we already *were* mucking with the types of ordered atomics and volatiles.  As a result, this change doesn't introduce as much new behavior as originally thought.

llvm-svn: 268809
2016-05-06 22:17:01 +00:00
Zachary Turner
375f9ee2b6 Make llvm-pdbdump print CV type records
This reuses the CVTypeDumper from libcodeview to dump full
information about type records within a PDB file.

Differential Revision: http://reviews.llvm.org/D20022
Reviewed By: rnk

llvm-svn: 268808
2016-05-06 22:15:42 +00:00
Kostya Serebryany
2583e597c6 [libFuzzer] add exeprimental -rss_limit_mb flag to fight against OOMs
llvm-svn: 268807
2016-05-06 21:58:35 +00:00
Justin Bogner
6d6bd1c06e CMake: generate check targets for lit suites without their own lit.cfgs
Currently our cmake generates targets like check-llvm-unit and
check-llvm-transforms-loopunroll-x86, but not check-llvm-transforms or
check-llvm-transforms-adce. This is because the search for test suites
only lists the ones with a custom lit.cfg or lit.local.cfg.

Instead, we can do something a little smarter - any directory under
test that isn't called Inputs or inside a directory called Inputs is a
test suite.

llvm-svn: 268806
2016-05-06 21:57:30 +00:00
Matthias Braun
9b767099e0 LiveIntervalAnalysis: Fix handleMove() extending liverange for undef inputs
Fix handleMove() incorrectly extending liveranges when an undef input of
a vreg was moved past the (current) end of the liverange.

llvm-svn: 268805
2016-05-06 21:47:41 +00:00
Philip Reames
751f932d9a [GVN] PRE of unordered loads
Again, fairly simple.  Only change is ensuring that we actually copy the property of the load correctly.  The aliasing legality constraints were already handled by the FRE patches.  There's nothing special about unorder atomics from the perspective of the PRE algorithm itself.

llvm-svn: 268804
2016-05-06 21:43:51 +00:00
Simon Pilgrim
e784303c41 [SLPVectorizer][X86] Added BSWAP/BITREVERSE vectorization tests
llvm-svn: 268803
2016-05-06 21:41:55 +00:00
Simon Pilgrim
0b1b8f9a44 [SLPVectorizer][X86] Added CTPOP/CTLZ/CTTZ vectorization tests
llvm-svn: 268800
2016-05-06 21:33:01 +00:00
Quentin Colombet
b57548ebe3 Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."
This reverts commit r268796.
I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with:
Cannot emit physreg copy instruction

llvm-svn: 268799
2016-05-06 21:21:50 +00:00
Zachary Turner
09bbd58bad Fix failing test due to merge conflict.
llvm-svn: 268798
2016-05-06 21:19:29 +00:00
Quentin Colombet
8fff738643 [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
The new register class reflects those constraints when choosing a
register class for a address access.

llvm-svn: 268796
2016-05-06 21:10:53 +00:00
Quentin Colombet
e9b1078e26 [X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS.
This register class may be used by any ABIs that uses x86_64 ISA while
using 32-bit addresses, not just in X32 cases. Make sure the name
reflects that.

llvm-svn: 268795
2016-05-06 21:10:43 +00:00
Nico Weber
76b0c74859 Revert r268760, it caused PR27670.
llvm-svn: 268794
2016-05-06 21:07:02 +00:00
Zachary Turner
37493811fd Add missing include.
llvm-svn: 268792
2016-05-06 20:59:35 +00:00
Zachary Turner
9a2aa250f9 Port DebugInfoPDB over to using llvm::Error.
Differential Revision: http://reviews.llvm.org/D19940
Reviewed By: rnk

llvm-svn: 268791
2016-05-06 20:51:57 +00:00
Sanjoy Das
4ad33c5c70 [RS4GC] Fix typo in comment
llvm-svn: 268790
2016-05-06 20:39:33 +00:00
Kevin Enderby
ee96ce6849 Change GenericBinaryError to no longer include a FileName, which is then not
part of the error message.

As the caller is the one that needs to add the name of where the "object file"
comes from to the error message as the object file could be in an archive, or
coming from a slice of a Mach-O universal file or a buffer created by a JIT.

In the cases of a Mach-O universal file the architecture name may or may not
also need to be printed which is up to the tool code.  For example if the tool
code is only selecting the host architecture slice then that architecture name
is never printed.

This patch is the change to the libObject code and there will be follow on
commits for changes to the code for each tool.

llvm-svn: 268789
2016-05-06 20:16:28 +00:00
Kostya Serebryany
b29cae8463 [libFuzzer] more trophies
llvm-svn: 268788
2016-05-06 20:14:48 +00:00
Ahmed Bougacha
b21c6806a5 [X86] Accept imp-defs of GR64 super-registers in FixupBW MOVrr.
Testcase will follow shortly.

llvm-svn: 268787
2016-05-06 20:03:03 +00:00
Marcin Koscielnicki
181dd83a14 [MSan] [X86] Fix vararg helper for fixed arguments in overflow area.
This fixes http://llvm.org/PR27646 on x86_64.

Differential Revision: http://reviews.llvm.org/D19997

llvm-svn: 268783
2016-05-06 19:36:56 +00:00
Artem Tamazov
d5f00a9b9b [AMDGPU][llvm-mc] Some refactoring of .td files
Some custom Operands and AsmOperandClasses moved to proper place.
No functional changes.

Differential Revision: http://reviews.llvm.org/D20012

llvm-svn: 268780
2016-05-06 19:32:38 +00:00
Adrian Prantl
4cae5e1ced Refactor the Verifier so it can diagnose IR validation errors and debug
info metadata errors separately. (NFC)

This patch refactors the Verifier so it can diagnose IR validation errors
and debug info metadata errors separately.
The motivation behind this change is that broken (or outdated) debug info
can be "recovered" from by stripping the debug info.

The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info.
We want to be able to make the verifier stricter without having to worry
about breaking bitcode compatibility with existing producers. For example,
we don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.

http://reviews.llvm.org/D19986
rdar://problem/25818489

llvm-svn: 268778
2016-05-06 19:26:47 +00:00
Krzysztof Parzyszek
37a28def86 [Hexagon] Be careful about anti-dependencies with a call in packetizer
In a case like
  J2_callr <ga:@foo>, %R0<imp-use>, ...
  R0<def> = ...
the anti-dependency on R0 cannot be ignored and the two instructions
cannot be packetized together, since if they were, the assignment to
R0 would take place before the call.

llvm-svn: 268776
2016-05-06 19:13:38 +00:00
Philip Reames
dc0f8cd8d4 [GVN] Handle unordered atomics in cross block FRE
You'll note there are essentially no code changes here.  Cross block FRE heavily reuses code from the block local FRE.  All of the tricky parts were done as part of the previous patch and the refactoring that removed the original code duplication.  

llvm-svn: 268775
2016-05-06 18:46:45 +00:00
Justin Bogner
a6d97fe150 SDAG: Don't leave dangling dead nodes after SelectCodeCommon
Relying on the caller to clean up after we've replaced all uses of a
node won't work when we've migrated to the `void Select(...)` API.

llvm-svn: 268774
2016-05-06 18:42:16 +00:00
Eric Christopher
52aaa2fdc5 The associated PR for this test was PR27135 not PR27132.
llvm-svn: 268772
2016-05-06 18:23:14 +00:00
Quentin Colombet
1c4bd3fb04 [X86] Get rid of X32_NOREX_ADDR_ACCESS register class.
According to H.J. Lu <hjl.tools@gmail.com>, this register class is never
used.

llvm-svn: 268771
2016-05-06 18:22:48 +00:00
Philip Reames
8b344ddfa7 [GVN] Do local FRE for unordered atomic loads
This patch is the first in a small series teaching GVN to optimize unordered loads aggressively. This change just handles block local FRE because that's the simplest thing which lets me test MDA, and the AvailableValue pieces. Somewhat suprisingly, MDA appears fine and only a couple of small changes are needed in GVN.

Once this is in, I'll tackle non-local FRE and PRE. The former looks like a natural extension of this, the later will require a couple of minor changes.

Differential Revision: http://reviews.llvm.org/D19440

llvm-svn: 268770
2016-05-06 18:17:13 +00:00
Mehdi Amini
e4d2c8bb3a Tweak the ThinLTO pass pipeline
Summary:
The original ThinLTO pipeline was derived from some
work I did tuning FullLTO on the test suite and SPEC. This
patch reduces the amount of work done in the "linker phase" of
the build, and extend the function simplifications passes
performed during the "compile phase". This helps the build time
by reducing the IR as much as possible during the compile phase
and limiting the work to be performed during the "link phase",
while keeping the performance "on par" with the existing pipeline.

Reviewers: tejohnson

Subscribers: llvm-commits, joker.eph

Differential Revision: http://reviews.llvm.org/D19773

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268769
2016-05-06 18:17:03 +00:00
Sanjay Patel
791dd3587c [SimplifyCFG] propagate branch metadata when creating select (retry r268550 / r268751 with possible fix)
Retrying r268550/r268751 which were reverted at r268577/r268765 due a memory sanitizer failure.
I have not been able to reproduce that failure, but I've taken another guess at fixing
the problem in this version of the patch and will watch for another failure.

Original commit message:
Unlike earlier similar fixes, we need to recalculate the branch weights
in this case.

Differential Revision: http://reviews.llvm.org/D19674

llvm-svn: 268767
2016-05-06 18:07:46 +00:00
Sanjay Patel
3ebfb989c8 revert r268751 - caused same failures on msan bot
llvm-svn: 268765
2016-05-06 17:51:37 +00:00
Simon Pilgrim
2ec2e6178f [CostModel][X86] Tweak 'SSE2-only' test CPU as it was only disabling SSE41 not SSE3/SSSE3 etc.
llvm-svn: 268763
2016-05-06 17:50:07 +00:00