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Commit Graph

130057 Commits

Author SHA1 Message Date
Xinliang David Li
bdfb6c9b6f Clean up test case
llvm-svn: 265887
2016-04-10 02:35:53 +00:00
Charles Davis
9f6526358e [CodeGen] Don't assume that fixed stack objects are aligned in a stack-realigned function.
Summary:
After we make the adjustment, we can assume that for local allocas, but
not for stack parameters, the return address, or any other fixed stack
object (which has a negative offset and therefore lies prior to the
adjusted SP).

Fixes PR26662.

Reviewers: hfinkel, qcolombet, rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D18471

llvm-svn: 265886
2016-04-09 23:34:42 +00:00
Davide Italiano
5f21656c16 [MC] support TLSDESC and TLSCALL / GNU2 tls dialect
Differential Revision:  http://reviews.llvm.org/D18885

llvm-svn: 265881
2016-04-09 20:32:33 +00:00
JF Bastien
16f8e8748e Fix hash_integer_value
Broken in D18938 because underlying_type only works for enums and not all stdlibs are sad when given a non-enum. Bots error out with 'only enumeration types have underlying types'.

There's probably a clever enable_if-ism that I can do with underlying_type and the actual integer value, but is_integral_or_enum also accepts implicit conversion so I need to ponder my life choices a bit before committing to template magic. A quick fix for now.

llvm-svn: 265880
2016-04-09 20:25:02 +00:00
JF Bastien
fd71b93500 is_integral_or_enum ❥ enum class ⇒ hashable enum class
Summary:
As discussed in D18775 making AtomicOrdering an enum class makes it non-hashable, which shouldn't be the case. Hashing.h defines hash_value for all is_integral_or_enum, but type_traits.h's definition of is_integral_or_enum only checks for *inplicit* conversion to integral types which leaves enum classes out and is very confusing because is_enum is true for enum classes.

This patch:
  - Adds a check for is_enum when determining is_integral_or_enum.
  - Explicitly converts the value parameter in hash_value to handle enum class hashing.

Note that the warning at the top of Hashing.h still applies: each execution of the program has a high probability of producing a different hash_code for a given input. Thus their values are not stable to save or persist, and should only be used during the execution for the construction of hashing datastructures.

Reviewers: dberlin, chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18938

llvm-svn: 265879
2016-04-09 20:04:34 +00:00
Adrian Prantl
c6dfc2642d Drop debug info for DISubprograms that are not referenced by anything
This patch drops the debug info for all DISubprograms that are
(a) not attached to an llvm::Function and
(b) not indirectly reachable via inline scopes from any surviving Function and
(c) not reachable from a type (i.e.: member functions).

Background: I'm currently working on a patch to reverse the pointers
between DICompileUnit and DISubprogram (for more info check Duncan's RFC
on lazy-loading of debug info metadata
http://lists.llvm.org/pipermail/llvm-dev/2016-March/097419.html).
The idea is to remove the list of subprograms from DICompileUnit and
instead point to the owning compile unit from each DISubprogram.
After doing this all DISubprograms fulfilling the above criteria will be
implicitly dropped unless we go through an extra effort to preserve them.

http://reviews.llvm.org/D18477
<rdar://problem/25256815>

llvm-svn: 265876
2016-04-09 18:10:22 +00:00
Sanjay Patel
ea5cc7e72d [x86] use BMI 'andn' for logic + compare ops
With BMI, we can use 'andn' to save an instruction when the result is only used in a compare.
This is related to one of the potential sequences to check 'isfinite' in:
https://llvm.org/bugs/show_bug.cgi?id=27164

Differential Revision: http://reviews.llvm.org/D18910

llvm-svn: 265875
2016-04-09 16:02:52 +00:00
Simon Pilgrim
c8f7b4ec60 [X86][XOP] Support for VPPERM 2-input shuffle mask decoding
This patch adds support for decoding XOP VPPERM instruction when it represents a basic shuffle.

The mask decoding required the existing MCInstrLowering code to be updated to support binary shuffles - the implementation now matches what is done in X86InstrComments.cpp.

Differential Revision: http://reviews.llvm.org/D18441

llvm-svn: 265874
2016-04-09 14:51:26 +00:00
Craig Topper
4d29234fe1 [X86] Use for loops over types to reduce code for setting up operation actions. NFC
llvm-svn: 265871
2016-04-09 06:31:02 +00:00
Craig Topper
cf77b72f78 [X86] Remove calls to setOperationAction that set CTLZ_ZERO_UNDEF for some vector types to Expand. Expand is already set for all operations for all vector types earlier so this is redundant. NFC
llvm-svn: 265870
2016-04-09 05:53:48 +00:00
Sanjoy Das
85af6d6f07 Maintain calling convention when inling calls to llvm.deoptimize
The behavior here was buggy -- we'd forget the calling convention after
inlining a callsite calling llvm.deoptimize.

llvm-svn: 265867
2016-04-09 00:22:59 +00:00
Mike Aizatsky
3b54b31344 [libfuzzer] defensive assert
llvm-svn: 265866
2016-04-08 23:32:24 +00:00
Chris Bieneman
918b321130 [CMake] Make llvm_ExternalProject always call the build action
This makes it so that when running 'ninja test-suite' from the top-level LLVM ninja build it *always* re-runs the ninja command in the test-suite directory.

This mechanism is required because the top-level ninja file doesn't have a view into the subdirectory dependency tree, so it can't know what, if anything, needs to be rebuilt.

llvm-svn: 265863
2016-04-08 22:46:04 +00:00
Adrian Prantl
4300f8a4c5 Support the Nodebug emission kind for DICompileUnits.
Sample-based profiling and optimization remarks currently remove
DICompileUnits from llvm.dbg.cu to suppress the emission of debug info
from them. This is somewhat of a hack and only borderline legal IR.

This patch uses the recently introduced NoDebug emission kind in
DICompileUnit to achieve the same result without breaking the Verifier.
A nice side-effect of this change is that it is now possible to combine
NoDebug and regular compile units under LTO.

http://reviews.llvm.org/D18808
<rdar://problem/25427165>

llvm-svn: 265861
2016-04-08 22:43:03 +00:00
Sanjay Patel
744e3da853 fix documentation comments; NFC
llvm-svn: 265855
2016-04-08 21:42:43 +00:00
Easwaran Raman
d28bd252a2 Refactor Threshold computation. NFC.
This is part of changes reviewed in http://reviews.llvm.org/D17584.

llvm-svn: 265852
2016-04-08 21:28:02 +00:00
Tim Shen
8cac1d5c28 [SSP] Remove llvm.stackprotectorcheck.
This is a cleanup patch for SSP support in LLVM. There is no functional change.
llvm.stackprotectorcheck is not needed, because SelectionDAG isn't
actually lowering it in SelectBasicBlock; rather, it adds check code in
FinishBasicBlock, ignoring the position where the intrinsic is inserted
(See FindSplitPointForStackProtector()).

llvm-svn: 265851
2016-04-08 21:26:31 +00:00
Sanjay Patel
9fcd4fe510 [x86] show missed opportunities to use andn
llvm-svn: 265850
2016-04-08 21:26:11 +00:00
Hans Wennborg
136b627c46 Rangeify a loop. NFC.
llvm-svn: 265846
2016-04-08 20:46:09 +00:00
Hans Wennborg
c3f3a07456 Remove some redundant variables from X86TargetLowering::LowerDYNAMIC_STACKALLOC
These are already defined, with the same values, a few lines up. NFC.

llvm-svn: 265845
2016-04-08 20:46:00 +00:00
Kyle Butt
0a6f26fc08 Codegen: Factor tail duplication into a utility class. NFC
This is in preparation for tail duplication during block placement. See D18226.
This needs to be a utility class for 2 reasons. No passes may run after block
placement, and also, tail-duplication affects subsequent layout decisions, so
it must be interleaved with placement, and can't be separated out into its own
pass. The original pass is still useful, and now runs by delegating to the
utility class.

llvm-svn: 265842
2016-04-08 20:35:01 +00:00
Sanjay Patel
a10f6f5022 [x86] regenerate checks for BMI tests
llvm-svn: 265841
2016-04-08 20:29:39 +00:00
Evgeny Stupachenko
eb50bea9cf test commit
llvm-svn: 265840
2016-04-08 20:20:38 +00:00
James Y Knight
dfd040c430 Add trailing colons to labels in a test.
This will avoid matching on the FILENAME if it happened to contain, say,
"f4" anywhere in the file path.

llvm-svn: 265837
2016-04-08 19:49:03 +00:00
Nirav Dave
7b6e012d2f Fix Load Control Dependence in MemCpy Generation
In Memcpy lowering we had missed a dependence from the load of the
operation to successor operations. This causes us to potentially
construct an in initial DAG with a memory dependence not fully
represented in the chain sub-DAG but rather require looking at the
entire DAG breaking alias analysis by allowing incorrect repositioning
of memory operations.

To work around this, r200033 changed DAGCombiner::GatherAllAliases to be
conservative if any possible issues to happen. Unfortunately this check
forbade many non-problematic situations as well. For example, it's
common for incoming argument lowering to add a non-aliasing load hanging
off of EntryNode. Then, if GatherAllAliases visited EntryNode, it would
find that other (unvisited) use of the EntryNode chain, and just give up
entirely. Furthermore, the check was incomplete: it would not actually
detect all such potentially problematic DAG constructions, because
GatherAllAliases did not guarantee to visit all chain nodes going up to
the root EntryNode. This is in general fine -- giving up early will just
miss a potential optimization, not generate incorrect results. But, for
this non-chain dependency detection code, it's possible that you could
have a load attached to a higher-up chain node than any which were
visited. If that load aliases your store, but the only dependency is
through the value operand of a non-aliasing store, it would've been
missed by this code, and potentially reordered.

With the dependence added, this check can be removed and Alias Analysis
can be much more aggressive. This fixes code quality regression in the
Consecutive Store Merge cleanup (D14834).

Test Change:

ppc64-align-long-double.ll now may see multiple serializations
of its stores

Differential Revision: http://reviews.llvm.org/D18062

llvm-svn: 265836
2016-04-08 19:44:40 +00:00
Duncan P. N. Exon Smith
436cc1b92b ValueMapper: Extract llvm::RemapFunction from IRMover.cpp, NFC
Strip out the remapping parts of IRLinker::linkFunctionBody and put them
in ValueMapper.cpp under the name Mapper::remapFunction (with a
top-level entry-point llvm::RemapFunction).

This is a nice cleanup on its own since it puts the remapping code
together and shares a single Mapper context for the entire
IRLinker::linkFunctionBody Call.  Besides that, this will make it easier
to break the co-recursion between IRMover.cpp and ValueMapper.cpp in
follow ups.

llvm-svn: 265835
2016-04-08 19:26:32 +00:00
Duncan P. N. Exon Smith
732203fd1c ValueMapper: Always use Mapper::mapValue from remapInstruction, NFCI
Use Mapper::mapValue instead of llvm::MapValue from
Mapper::remapInstruction when mapping an incoming block for a PHINode
(follow-up to r265832).  This will implicitly pass along the
Materializer argument, but when this code was added in r133513 there was
no Materializer argument.  I suspect this call to MapValue was just
missed in r182776 since it's not observable (basic blocks can't be
materialized, and they don't reference other values).

llvm-svn: 265833
2016-04-08 19:17:13 +00:00
Duncan P. N. Exon Smith
61b07b7af9 ValueMapper: Roll RemapInstruction into Mapper, NFC
Add Mapper::remapInstruction, move the guts of llvm::RemapInstruction
into it, and use the same Mapper for most of the calls to MapValue and
MapMetadata.  There should be no functionality change here.

I left off the call to MapValue that wasn't passing in a Materializer
argument (for basic blocks of PHINodes).  It shouldn't change
functionality either, but I'm suspicious enough to commit separately.

llvm-svn: 265832
2016-04-08 19:09:34 +00:00
Duncan P. N. Exon Smith
743f6706d4 Linker: Always pass RF_IgnoreMissingLocals; NFC
This is a cleanup after clarifying the meaning of RF_IgnoreMissingLocals
in r265628 and truly limiting it to locals in r265768.

This should have no functionality change, since the only context that
the flag has an effect is when we could hit function-local Value and
Metadata, and we were already passing it in those contexts.

llvm-svn: 265831
2016-04-08 19:01:38 +00:00
Kevin B. Smith
5defc888fe [X86] Fix PR23155 by turning on X86FixupBWInsts by default.
Differential Revision: http://reviews.llvm.org/D18866

llvm-svn: 265830
2016-04-08 18:58:29 +00:00
Duncan P. N. Exon Smith
695a2ff629 ValueMapper: Don't memoize metadata when RF_NoModuleLevelChanges
Prevent the Metadata side-table in ValueMap from growing unnecessarily
when RF_NoModuleLevelChanges.  As a drive-by, make ValueMap::hasMD,
which apparently had no users until I used it here for testing, actually
compile.

llvm-svn: 265828
2016-04-08 18:49:36 +00:00
Duncan P. N. Exon Smith
238a64e1c5 ValueMapper: Stop memoizing MDStrings
Stop adding MDString to the Metadata section of the ValueMap in
MapMetadata.  It blows up the size of the map for no benefit, since we
can always return quickly anyway.

There is a potential follow-up that I don't think I'll push on right
away, but maybe someone else is interested:  stop checking for a
pre-mapped MDString, and move the `isa<MDString>()` checks in
Mapper::mapSimpleMetadata and MDNodeMapper::getMappedOp in front of the
`VM.getMappedMD()` calls.  While this would preclude explicitly
remapping MDStrings it would probably be a little faster.

llvm-svn: 265827
2016-04-08 18:47:02 +00:00
Sanjoy Das
224e72eaad Propagate Undef in llvm.cos Intrinsic
Summary:
The llvm cos intrinsic currently does not propagate undef's. This change
transforms cos(undef) to null value or 0.

There are 2 test cases added as well.

Patch by Anna Thomas!

Reviewers: sanjoy

Subscribers: majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D18863

llvm-svn: 265825
2016-04-08 18:21:11 +00:00
Colin LeMahieu
ed62b97b18 Revert r265817
lld tests need to be addressed.

llvm-svn: 265822
2016-04-08 18:15:37 +00:00
Colin LeMahieu
eaba356a61 [llvm-objdump] Printing hex instead of dec by default
Differential Revision: http://reviews.llvm.org/D18770

llvm-svn: 265817
2016-04-08 17:55:03 +00:00
Lang Hames
28d2b8f458 [Object] Report an error if .alt_entry is used with ELF or COFF.
I'm looking into a better way to do this long-term, but for now at least don't
crash.

llvm-svn: 265815
2016-04-08 17:38:51 +00:00
Ulrich Weigand
7102a6833f [SystemZ] Support conditional sibling calls via BRCL
This adds a conditional variant of CallJG instruction, CallBRCL.
It can be used for conditional sibling calls. Unfortunately, due
to IfCvt limitations, it only really works well for functions without
arguments.

Author: koriakin
Differential Revision: http://reviews.llvm.org/D18864

llvm-svn: 265814
2016-04-08 17:22:19 +00:00
Quentin Colombet
c960359680 [RegBankSelect] Use reverse post order traversal.
When assigning the register banks of an instruction, it is best to know
all the constraints of the input to have a good idea of how this will
impact the cost of the whole function.

llvm-svn: 265812
2016-04-08 17:19:10 +00:00
Quentin Colombet
9795e49e82 [AArch64] Add a test case for the default mapping of RegBankSelect.
llvm-svn: 265811
2016-04-08 17:11:51 +00:00
Quentin Colombet
d094c81fdc [RegisterBankInfo] Change the implementation for the default mapping.
Do not give that much importance to the current register bank of an
operand. This is likely just a side effect of the current execution and
it is properly wise to prefer a register bank that can be extracted from
the information available statically (like encoding constraints and
type).

llvm-svn: 265810
2016-04-08 16:59:50 +00:00
David Majnemer
08e9ca8730 [InstCombine] Fix miscompile in FoldSPFofSPF
We had a select of a cast of a select but attempted to replace the outer
select with the inner select dispite their incompatible types.

Patch by Anton Korobeynikov!

This fixes PR27236.

llvm-svn: 265805
2016-04-08 16:51:49 +00:00
Quentin Colombet
d32719b8ce [RegBankSelect] Improve debug output.
Add verbose information when checking if the current and the desired
register banks match.
Detail what happens when we assign a register bank.

llvm-svn: 265804
2016-04-08 16:48:16 +00:00
Mehdi Amini
ccab635f5a Fix missing include on OpenBSD
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265803
2016-04-08 16:45:05 +00:00
Quentin Colombet
6fa8f3c563 [MIR] Teach the parser how to deal with register banks.
llvm-svn: 265802
2016-04-08 16:40:43 +00:00
David Majnemer
8f75cadbc7 [InstCombine] Add a peephole for redundant assumes
Two or more identical assumes are occasionally next to each other in a
basic block.
While our generic machinery will turn a redundant assume into a no-op,
it is not super cheap.
We can perform a simpler check to achieve the same result for this case.

llvm-svn: 265801
2016-04-08 16:37:12 +00:00
David Majnemer
a4716b737d [LoopVectorize] Register cloned assumptions
InstCombine cannot effectively remove redundant assumptions without them
registered in the assumption cache.  The vectorizer can create identical
assumptions but doesn't register them with the cache, resulting in
slower compile times because InstCombine tries to reason about a lot
more assumptions.

Fix this by registering the cloned assumptions.

llvm-svn: 265800
2016-04-08 16:37:10 +00:00
Quentin Colombet
a1ab58869e [MachineVerifier] Teach how to check some of the properties of generic
virtual registers.

Generic virtual registers:
- May not have a register class
- May not have a register bank
- If they do not have a register class they must have a size
- If they have a register bank, the size of the register bank must be
  greater or equal to the size of the virtual register (basically check
  that the virtual register will fit into that register class)

llvm-svn: 265798
2016-04-08 16:35:22 +00:00
Quentin Colombet
41d753beef [MIR] Teach the mir printer how to print the register bank.
For now, we put the register bank in the Class field since a register
may only have one of those at a given time. The downside of that
representation is that if a register class and a register bank have the
same name, we will not be able to distinguish them.

llvm-svn: 265796
2016-04-08 16:26:22 +00:00
Sam Parker
e40fc81f76 [ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection
Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt,
smulwb and smulwt instructions for the ARM backend. Also updated the smul
CodeGen test and removed the smulw one.

Differential Revision: http://reviews.llvm.org/D18892

llvm-svn: 265793
2016-04-08 16:02:53 +00:00
Hans Wennborg
8c75bb0137 Revert r265547 "Recommit r265309 after fixed an invalid memory reference bug happened"
It caused PR27275: "ARM: Bad machine code: Using an undefined physical register"

Also reverting the following commits that were landed on top:
r265610 "Fix the compare-clang diff error introduced by r265547."
r265639 "Fix the sanitizer bootstrap error in r265547."
r265657 "InlineSpiller.cpp: Escap \@ in r265547. [-Wdocumentation]"

llvm-svn: 265790
2016-04-08 15:17:43 +00:00