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Commit Graph

199315 Commits

Author SHA1 Message Date
Paul Walker
2467d01420 [SVE] Code generation for fixed length vector adds.
Summary:
Teach LowerToPredicatedOp to lower fixed length vector operations.

Add AArch64ISD nodes and isel patterns for predicated integer
and floating point adds.

Together this enables SVE code generation for fixed length vector adds.

Reviewers: rengolin, efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82483
2020-06-26 19:54:41 +00:00
Roman Lebedev
1167cf8023 [CostModel] Avoid traditional ConstantExpr crashy pitfails
I'm not sure if this is a regression from D81448 + D81643,
which moved at least the code cast from elsewhere,
or somehow no one triggered that before.
But now we can reach it with a non-instruction..

It is not straight-forward to write cost-model tests for constantexprs,
`-cost-model -analyze -cost-kind=` does not appear to look at them,
or maybe i'm doing it wrong.

I've encountered that via a SimplifyCFG crash,
so reduced (currently-crashing) test is added.
There are likely other instances.

For now, simply restore previous status quo of
not crashing and returning TTI::TCC_Basic.
2020-06-26 22:48:10 +03:00
Matt Arsenault
5127ccf75b AMDGPU: Add llvm.amdgcn.sqrt intrinsic
I spread the GlobalISel test into the regular one, which I've been
avoiding so far.
2020-06-26 15:07:07 -04:00
David Tenty
339a41084d [NFCI] Cleanup range checks in Register/MCRegister
Summary:
by removing casts from unsigned to int that which may be implementation
defined according to C++14 (and thus trip up the XL compiler on AIX) by
just using unsigned comparisons/masks and refactor out the range
constants to cleanup things a bit while we are at it.

Reviewers: hubert.reinterpretcast, arsenm

Reviewed By: hubert.reinterpretcast

Subscribers: wdng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82197
2020-06-26 14:55:55 -04:00
Sanjay Patel
2fca4fc03f [DAGCombiner] rename variables for readability; NFC
PR46406 shows a pattern where we can do better, so try to clean this up
before adding more code.
2020-06-26 14:22:11 -04:00
Sanjay Patel
5dcf739606 [AArch64] add vector test for merged condition branching; NFC 2020-06-26 14:22:11 -04:00
Amy Kwan
04ae1ab1c3 [PowerPC] Add support for llvm.ppc.dcbt, llvm.ppc.dcbtst, llvm.ppc.isync intrinsics
This patch adds LLVM intrinsics for the dcbt (Data Cache Block Touch),
dcbtst (Data Cache Block Touch for Store) and isync (Instruction
Synchronize) instructions.

The intrinsic for dcbt and dcbst in this patch are named llvm.ppc.dcbt.with.hint
and llvm.ppc.dcbtst.with.hint respectively as there already exists an intrinsic
for llvm.ppc.dcbt and llvm.ppc.dcbtst. However, the original variants of the
intrinsics do not accept the TH immediate field, whereas these variants do.

Differential Revision: https://reviews.llvm.org/D79633
2020-06-26 13:02:18 -05:00
Rong Xu
14ba3c75bf [PGO] Add a functionality to always instrument the func entry BB
Add an option to always instrument function entry BB (default off)
Add an option to do atomically updates on the first counter in each
instrumented function.

Differential Revision: https://reviews.llvm.org/D82123
2020-06-26 10:43:23 -07:00
Philip Reames
23dcf5ab2d Migrate last batch of tests to gc-live bundle format
For context of anyone following along, we've not completed the migration of statepoint to the operand bundle form.  The only remaining piece is to actually version the statepoint intrinsic to remove the old inline operand sets.  That will follow when I have some time; delay is useful here to allow downstream migrations.
2020-06-26 10:28:27 -07:00
Nico Weber
786f34e738 Revert "[clang driver] Move default module cache from system temporary directory"
This reverts commit bb26838ceffb5feaa18186f55f7525a08084899e.
Breaks Support.CacheDirectoryNoEnv, Support.CacheDirectoryWithEnv
in SupportTests (part of check-llvm) on macOS.
2020-06-26 13:25:45 -04:00
Arthur Eubanks
2658ebda83 [NewPM][LoopUnroll] Rename unroll* to loop-unroll*
The legacy pass is called "loop-unroll", but in the new PM it's called "unroll".
Also applied to unroll-and-jam and unroll-full.

Fixes various check-llvm tests when NPM is turned on.

Reviewed By: Whitney, dmgreen

Differential Revision: https://reviews.llvm.org/D82590
2020-06-26 09:28:32 -07:00
Kit Barton
bb26f5df42 [PPC][NFC] Add Subtarget and replace all uses of PPCSubTarget with Subtarget.
Summary:
In preparation for GlobalISel, PPCSubTarget needs to be renamed to Subtarget as there places in GlobalISel that assume the presence of the variable Subtarget.
This patch introduces the variable Subtarget, and replaces all existing uses of PPCSubTarget with Subtarget. A subsequent patch will remove the definiton of
PPCSubTarget, once any downstream users have the opportunity to rename any uses they have.

Reviewers: hfinkel, nemanjai, jhibbits, #powerpc, echristo, lkail

Reviewed By: #powerpc, echristo, lkail

Subscribers: echristo, lkail, wuzish, nemanjai, hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81623
2020-06-26 11:23:38 -05:00
sstefan1
9111261e00 [OpenMPOpt][NFC] Change ICV macros for initial value
This fixes build breaks when system headers are difining FALSE.
2020-06-26 15:34:43 +00:00
Francesco Petrogalli
fb4e03c951 [sve][acle] Add reinterpret intrinsics for brain float.
Reviewers: kmclaughlin, efriedma, ctetreau, sdesmalen, david-arm

Subscribers: tschuett, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82501
2020-06-26 15:20:58 +00:00
Vy Nguyen
052f666a48 [llvm-exegesis] Let Counter returns up to 16 entries
LBR contains (up to) 16 entries for last x branches and the X86LBRCounter (from D77422) should be able to return all those.
    Currently, it just returns the latest entry, which could lead to mis-leading measurements.
    This patch aslo changes the LatencyBenchmarkRunner to accommodate multi-value readings.

         https://reviews.llvm.org/D81050
2020-06-26 10:57:20 -04:00
Guillaume Chatelet
61be63afc4 [Alignment][NFC] Migrate TTI::isLegalToVectorize{Load,Store}Chain to Align
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82653
2020-06-26 14:14:27 +00:00
Matt Arsenault
5d95ec786c AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI
This had an extra attempt to align the pointer, which only did
anything with a base kernel argument offset which only clover used to
use.
2020-06-26 10:03:05 -04:00
Matt Arsenault
487f0631b0 AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI
I'm not sure we actually need to support this now, since I think
clover always explicitly uses amdgcn-mesa-mesa3d now, not the
ill-defined amdgcn-- behavior.
2020-06-26 10:03:05 -04:00
Matt Arsenault
e98f5892d2 AMDGPU/GlobalISel: Uncomment some fixed tests 2020-06-26 10:03:05 -04:00
Kerry McLaughlin
8b3ff6c213 [AArch64][SVE] Remove asserts from AArch64ISelLowering for bfloat16 types
Remove the asserts in performLDNT1Combine & performST[NT]1Combine
to ensure we get a failure where the type is a bfloat16 and
hasBF16() is false, regardless of whether asserts are enabled.
2020-06-26 14:51:27 +01:00
serge-sans-paille
d14affcd91 Fix pass return status for loop extractor
As loop extractor has a dependency on another pass (namely BreakCriticalEdges)
that may update the IR, use the getAnalysis version introduced in
55fe7b79bb7fab49af3720840224c0720bdb03c6 to carry that change.

Add an assert in getAnalysisID to make sure no other changed status is missed -
according to validation this was the only one.

Related to https://reviews.llvm.org/D80916

Differential Revision: https://reviews.llvm.org/D81236
2020-06-26 15:49:27 +02:00
Simon Pilgrim
f5fa275b44 Revert rGf0bab7875e78e01c149d12302dcc4b6d4c43e25c - "Triple.h - reduce Twine.h include to forward declarations. NFC."
This causes ICEs on the clang-ppc64be buildbots and I've limited ability to triage the problem.
2020-06-26 14:46:40 +01:00
Simon Pilgrim
08eb1e1f85 Add explicit Twine.h include to try and fix ICE on clang-ppc64be-linux 2020-06-26 14:14:09 +01:00
Simon Tatham
24333be966 Fix implicit include dependencies on SmallVector.h.
Both `AArch64TargetParser.h` and `ARMTargetParser.h` refer to
`SmallVectorImpl` without directly including the header that defines
it, which works fine until nothing else happens to include it anyway.
2020-06-26 13:49:17 +01:00
Cullen Rhodes
83a117d0a9 [AArch64][SVE] Only support sizeless bfloat types if supported by subtarget
Reviewers: sdesmalen, efriedma, kmclaughlin, fpetrogalli

Reviewed By: sdesmalen, fpetrogalli

Differential Revision: https://reviews.llvm.org/D82494
2020-06-26 12:37:47 +00:00
Anatoly Trosinenko
741830615d [MSP430] Update register names
When writing a unit test on replacing standard epilogue sequences with `BR __mspabi_func_epilog_<N>`, by manually asm-clobbering `rN` - `r10` for N = 4..10, everything worked well except for seeming inability to clobber r4.

The problem was that MSP430 code generator of LLVM used an obsolete name FP for that register. Things were worse because when `llc` read an unknown register name, it silently ignored it.

That is, I cannot use `fp` register name from the C code because Clang does not accept it (exactly like GCC). But the accepted name `r4` is not recognised by `llc` (it can be used in listings passed to `llvm-mc` and even `fp` is replace to `r4` by `llvm-mc`). So I can specify any of `fp` or `r4` for the string literal of `asm(...)` but nothing in the clobber list.

This patch replaces `MSP430::FP` with `MSP430::R4` in the backend code (even [MSP430 EABI](http://www.ti.com/lit/an/slaa534/slaa534.pdf) doesn't mention FP as a register name). The R0 - R3 registers, on the other hand, are left as is in the backend code (after all, they have some special meaning on the ISA level). It is just ensured clang is renaming them as expected by the downstream tools. There is probably not much sense in **marking them clobbered** but rename them //just in case// for use at potentially different contexts.

Differential Revision: https://reviews.llvm.org/D82184
2020-06-26 15:32:07 +03:00
serge-sans-paille
8ab1269af8 Improve LegacyPassManager API to correctly report modified status
When calling on-the-fly passes from the legacy pass manager, the modification
status is not reported, which is a problem in case we depend on an acutal
transformation pass, and not only analyse.

Update the Legacy PM API to optionally report the changed status, assert if a
change is detected but this change is lost.

Related to https://reviews.llvm.org/D80916

Differential Revision: https://reviews.llvm.org/D81236
2020-06-26 14:21:02 +02:00
Simon Pilgrim
efd7ae7bbc Triple.h - reduce Twine.h include to forward declarations. NFC.
Move include down to a number of other files that had an implicit dependency on the Twine class.
2020-06-26 13:06:57 +01:00
David Zarzycki
1d3f54691c [clang driver] Move default module cache from system temporary directory
1) Shared writable directories like /tmp are a security problem.
2) Systems provide dedicated cache directories these days anyway.
3) This also refines LLVM's cache_directory() on Darwin platforms to use
   the Darwin per-user cache directory.

Reviewers: compnerd, aprantl, jakehehrlich, espindola, respindola, ilya-biryukov, pcc, sammccall

Reviewed By: compnerd, sammccall

Subscribers: hiraditya, llvm-commits, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82362
2020-06-26 07:46:03 -04:00
Simon Pilgrim
e8162e21bd TargetSubtargetInfo.h - remove unnecessary forward declarations. NFC.
We have to include MCSubtargetInfo.h
2020-06-26 12:30:15 +01:00
Simon Pilgrim
2fb2d48ab9 MemorySSAUpdater.h - remove unnecessary WeakVH forward declaration. NFC.
We have to include ValueHandle.h
2020-06-26 12:30:14 +01:00
Xing GUO
2dbd7a6f26 [DWARFYAML][debug_info] Teach yaml2obj emit correct DWARF64 unit header.
This patch helps teach yaml2obj emit correct DWARF64 unit header of the .debug_info section.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D82621
2020-06-26 19:25:26 +08:00
Guillaume Chatelet
0a9a5ce8bf [Alignment][NFC] Migrate TTI::getGatherScatterOpCost to Align
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82577
2020-06-26 11:08:27 +00:00
Guillaume Chatelet
9470341223 [Alignment][NFC] Migrate TTI::getInterleavedMemoryOpCost to Align
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82573
2020-06-26 11:00:53 +00:00
Jay Foad
b414fc0de1 [AMDGPU] Use std::pair to return two values. NFC. 2020-06-26 11:47:12 +01:00
Guillaume Chatelet
0a29dd919f [Alignment][NFC] Migrate TTI::getMaskedMemoryOpCost to Align
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82569
2020-06-26 10:14:16 +00:00
Kerry McLaughlin
eb10451902 [AArch64][SVE] Add bfloat16 support to store intrinsics
Summary:
Bfloat16 support added for the following intrinsics:
 - ST1
 - STNT1

Reviewers: sdesmalen, c-rhodes, fpetrogalli, efriedma, stuij, david-arm

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82448
2020-06-26 11:05:56 +01:00
Simon Pilgrim
2a4dbacbc5 LoopVectorize.h - reduce AliasAnalysis.h include to forward declaration. NFC.
Replace legacy AliasAnalysis typedef with AAResults where necessary.
2020-06-26 10:49:00 +01:00
Kerry McLaughlin
c4cb941ff9 [AArch64][SVE] Predicate bfloat16 load patterns with HasBF16
Reviewers: sdesmalen, c-rhodes, efriedma, fpetrogalli

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82464
2020-06-26 10:38:24 +01:00
Cullen Rhodes
af0ff0941f [AArch64][SVE] Guard perm and select bfloat16 intrinsic patterns
Summary:
Permutation and selection bfloat16 intrinsic patterns should be guarded
on the feature flag `+bf16`. Missed in D82182 and D80850.

Reviewers: sdesmalen, fpetrogalli, kmclaughlin, efriedma

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D82492
2020-06-26 09:35:36 +00:00
David Green
33b3ee4e0a [ARM] VCVTT fpround instruction selection
Similar to the recent patch for fpext, this adds vcvtb and vcvtt with
insert into vector instruction selection patterns for fptruncs. This
helps clear up a lot of register shuffling that we would otherwise do.

Differential Revision: https://reviews.llvm.org/D81637
2020-06-26 10:24:06 +01:00
Simon Pilgrim
3705e589ad Constants.h - remove unnecessary forward declarations. NFC.
We have to include DerivedTypes.h
2020-06-26 09:58:22 +01:00
Simon Pilgrim
07b2d5cea2 MemoryLocation.h - reduce Instruction.h include to forward declaration. NFC. 2020-06-26 09:58:21 +01:00
Simon Pilgrim
2a154d7b05 LiveRangeEdit.h - reduce AliasAnalysis.h include to forward declaration. NFC.
Move include to LiveRangeEdit.cpp and replace legacy AliasAnalysis typedef with AAResults where necessary.
2020-06-26 09:58:21 +01:00
Simon Pilgrim
44a4cd8a40 Fix some clang-tidy namespace closing comments warnings. NFC. 2020-06-26 09:58:21 +01:00
Simon Pilgrim
04f40220e9 VNCoercion.cpp - remove unused includes. NFC. 2020-06-26 09:58:20 +01:00
Simon Pilgrim
817a219e4e AggressiveInstCombineInternal.h - reduce unnecessary includes to forward declarations. NFC. 2020-06-26 09:58:20 +01:00
David Green
6ea3fc012b [ARM] VCVTT instruction selection
We current extract and convert from a top lane of a f16 vector using a
VMOVX;VCVTB pair. We can simplify that to use a single VCVTT. The
pattern is mostly copied from a vector extract pattern, but produces a
VCVTTHS f32 directly.

This had to move some code around so that ARMInstrVFP had access to the
required pattern frags that were previously part of ARMInstrNEON.

Differential Revision: https://reviews.llvm.org/D81556
2020-06-26 08:58:55 +01:00
Craig Topper
f05f07a9a2 [X86] Make XSAVEC/XSAVEOPT/XSAVES properly depend on XSAVE in both the frontend and the backend.
These features implicitly enabled XSAVE in the frontend, but not
the backend. Disabling XSAVE in the frontend disabled XSAVEOPT, but
not the other 2. Nothing happened in the backend.
2020-06-26 00:14:58 -07:00
David Sherwood
a93ac100b1 [SVE] Fix scalable vector bug in DataLayout::getIntPtrType
Fixed an issue in DataLayout::getIntPtrType where we were assuming
the input type was always a fixed vector type, which isn't true.

Added a test that exposed the problem to:

  Transforms/InstCombine/vector_gep1.ll

Differential Revision: https://reviews.llvm.org/D82294
2020-06-26 07:58:45 +01:00