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Commit Graph

56 Commits

Author SHA1 Message Date
Jim Grosbach
2b81a07dc7 Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890

llvm-svn: 112241
2010-08-26 23:32:16 +00:00
Rafael Espindola
9113809536 cleanup
llvm-svn: 105322
2010-06-02 13:53:17 +00:00
Jim Grosbach
f328c5334f Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

llvm-svn: 98086
2010-03-09 21:45:49 +00:00
David Greene
9934b1d063 Make the MachineFunction argument of getFrameRegister const.
This also fixes a build error.

llvm-svn: 87027
2009-11-12 21:00:03 +00:00
Jim Grosbach
61c5ce1bde Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467
2009-10-07 17:12:56 +00:00
Chris Lattner
18af1b233a Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.

llvm-svn: 77501
2009-07-29 20:31:52 +00:00
Tilmann Scheller
37389b484a Implement the SVR4 ABI for PowerPC.
Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.

llvm-svn: 74765
2009-07-03 06:45:56 +00:00
Evan Cheng
e00df1d39c Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
llvm-svn: 63938
2009-02-06 17:43:24 +00:00
Evan Cheng
38a755499d Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Bill Wendling
8d64999daf This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863
2008-03-03 22:19:16 +00:00
Dan Gohman
cabaec582f Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Owen Anderson
f19692b2f6 Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Owen Anderson
e6856128ab Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Chris Lattner
1024cda0bd refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things.  Document what the
one in PPCFunctionInfo means and when it is valid.

llvm-svn: 44699
2007-12-08 06:39:11 +00:00
Evan Cheng
27986f1ac7 Added canFoldMemoryOperand for PPC.
llvm-svn: 44623
2007-12-05 18:41:29 +00:00
Evan Cheng
8464a0bf00 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.

llvm-svn: 44600
2007-12-05 03:14:33 +00:00
Evan Cheng
58b387dfb0 Remove redundant foldMemoryOperand variants and other code clean up.
llvm-svn: 44517
2007-12-02 08:30:39 +00:00
Evan Cheng
79e8b92dc3 Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
llvm-svn: 44479
2007-12-01 02:07:52 +00:00
Dale Johannesen
5fd9e7a615 Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056
2007-11-13 19:13:01 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
2007-11-11 19:50:10 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.

llvm-svn: 43153
2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
Evan Cheng
f536e2f41e - Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
2007-10-05 01:32:41 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!

llvm-svn: 42346
2007-09-26 06:25:56 +00:00
Evan Cheng
58ea935f6f Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
llvm-svn: 41597
2007-08-30 05:52:20 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
2007-07-14 14:06:15 +00:00
Evan Cheng
e47ec4d104 eliminateFrameIndex() change.
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction.
llvm-svn: 35205
2007-03-20 08:09:38 +00:00
Evan Cheng
b0c0d22f30 Minor interface change.
llvm-svn: 34967
2007-03-06 10:05:14 +00:00
Evan Cheng
116f97f2c7 PEI now passes a RegScavenger ptr to eliminateFrameIndex.
llvm-svn: 34707
2007-02-28 00:21:17 +00:00
Jim Laskey
f5b5a3cf77 Duplicate use of LR, take 2.
llvm-svn: 34666
2007-02-27 11:55:45 +00:00
Evan Cheng
f54dbab209 Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29

llvm-svn: 34652
2007-02-27 02:55:29 +00:00
Jim Laskey
704423b797 Don't spill LR as a callee saved register.
llvm-svn: 34533
2007-02-23 20:34:16 +00:00
Jim Laskey
6a937ad320 Support to provide exception and selector registers.
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
Evan Cheng
e4ab9c032b Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482 For PR1207:
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399
2007-02-19 03:20:00 +00:00
Evan Cheng
8c2508f1ac Added getReservedRegs().
llvm-svn: 34376
2007-02-17 11:06:00 +00:00
Evan Cheng
9009b02367 - Tell PEI that PPC will handle stack frame rounding itself.
- Do not round up to max. alignment of stack object if it is > stack alignment.
  It will have to be handled with dynamic aligning code.

llvm-svn: 33505
2007-01-25 22:25:04 +00:00
Jim Laskey
a67f14502d Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)

llvm-svn: 33488
2007-01-24 18:45:13 +00:00
Evan Cheng
d9d93832b0 hasFP() is now a virtual method of MRegisterInfo.
llvm-svn: 33455
2007-01-23 00:57:47 +00:00
Evan Cheng
bd6a333b52 Fix naming inconsistency.
llvm-svn: 32823
2007-01-02 21:33:40 +00:00
Jim Laskey
0ffc5bc871 Make it easier for gdb to find the return address.
llvm-svn: 32277
2006-12-06 17:42:06 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.

llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Jim Laskey
8aac7dc0ee This is a general clean up of the PowerPC ABI. Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792
2006-11-16 22:43:37 +00:00
Evan Cheng
0e82270ff2 Matches MachineInstr changes.
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
Chris Lattner
2db97248f8 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
llvm-svn: 29096
2006-07-11 00:48:23 +00:00
Evan Cheng
667b133ab9 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Chris Lattner
6b76deffb5 Move some knowledge about registers out of the code emitter into the register info.
llvm-svn: 27770
2006-04-17 21:07:20 +00:00