1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
Commit Graph

154094 Commits

Author SHA1 Message Date
Sanjay Patel
5be0f20311 [InstSimplify] add tests for possible sdiv/srem simplifications; NFC
As noted in PR34517, the handling of signed div/rem is not on par with
unsigned div/rem. Signed is harder to reason about, but it should be
possible to handle at least some of these using the same technique that
we use for unsigned: use icmp logic to see if there's a relationship
between the quotient and divisor.

llvm-svn: 312938
2017-09-11 19:42:41 +00:00
Matt Arsenault
c6fab4ecd2 AMDGPU: Allow coldcc calls
llvm-svn: 312936
2017-09-11 18:54:20 +00:00
Petar Jovanovic
a5ac789396 [mips][microMIPS] add lapc instruction
Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D35984

llvm-svn: 312934
2017-09-11 18:34:04 +00:00
Hiroshi Yamauchi
9745453d49 Unmerge GEPs to reduce register pressure on IndirectBr edges.
Summary:
GEP merging can sometimes increase the number of live values and register
pressure across control edges and cause performance problems particularly if the
increased register pressure results in spills.

This change implements GEP unmerging around an IndirectBr in certain cases to
mitigate the issue. This is in the CodeGenPrepare pass (after all the GEP
merging has happened.)

With this patch, the Python interpreter loop runs faster by ~5%.

Reviewers: sanjoy, hfinkel

Reviewed By: hfinkel

Subscribers: eastig, junbuml, llvm-commits

Differential Revision: https://reviews.llvm.org/D36772

llvm-svn: 312930
2017-09-11 17:52:08 +00:00
Stanislav Mekhanoshin
ac399c356c [AMDGPU] Produce madak and madmk from the two-address pass
These two instructions are normally selected, but when the
two address pass converts mac into mad we end up with the
mad where we could have one of these.

Differential Revision: https://reviews.llvm.org/D37389

llvm-svn: 312928
2017-09-11 17:13:57 +00:00
Craig Topper
c923b2dacd [X86] Remove portions of r275950 that are no longer needed with i1 not being a legal type
Summary:
r275950 added support for turning (trunc (X >> N) to i1) into BT(X, N). But that's no longer necessary now that i1 isn't legal.

This patch removes the support for that, but preserves some of the refactorings done in that commit.

Reviewers: guyblank, RKSimon, spatel, zvi

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37673

llvm-svn: 312925
2017-09-11 16:16:48 +00:00
Craig Topper
35171f5693 [SelectionDAG] Remove a check for type being a vector type after calling getShiftAmountTy. NFCI
getShiftAmountTy already returns the vector type when called for vectors.

llvm-svn: 312924
2017-09-11 16:15:39 +00:00
Zvi Rackover
ff2fa68816 X86 Tests: More AVX512 conversions tests. NFC
Adding more tests for AVX512 fp<->int conversions that were missing.

llvm-svn: 312921
2017-09-11 15:54:38 +00:00
Marcello Maggioni
a5112a6088 [ScalarEvolution] Refactor forgetLoop() to improve performance
forgetLoop() has pretty bad performance because it goes over
the same instructions over and over again in particular when
nested loop are involved.
The refactoring changes the function to a not-recursive function
and reusing the allocation for data-structures and the Visited
set.

NFCI

Differential Revision: https://reviews.llvm.org/D37659

llvm-svn: 312920
2017-09-11 15:44:20 +00:00
Matt Arsenault
f9c535762c Fix typo
llvm-svn: 312919
2017-09-11 15:23:22 +00:00
Simon Pilgrim
8beb4573f2 [X86][SSE] Add support for X86ISD::PACKSS to ComputeNumSignBitsForTargetNode
Helps improve combineLogicBlendIntoPBLENDV support by allowing us to peek into through PACKSS truncations of vector comparison results.

Differential Revision: https://reviews.llvm.org/D37680

llvm-svn: 312916
2017-09-11 14:03:47 +00:00
Tim Renouf
0ce7d42fef [AMDGPU] exp should not be in WQM mode
A mrt exp with vm=1 must be in exact (non-WQM) mode, as it also exports
the exec mask as the valid mask to determine which pixels to render.

This commit marks any exp as needing to be in exact mode.

Actually, if there are multiple mrt exps, only one needs to have vm=1,
and only that one needs to be in exact mode. But that is an optimization
for another day.

Differential Revision: https://reviews.llvm.org/D36305

llvm-svn: 312915
2017-09-11 13:55:39 +00:00
Francis Ricci
e565155f20 [TableGen] Ensure that __lsan_is_turned_off isn't removed by DCE in llvm-tblgen
Summary:
Since asan is linked dynamically on Darwin, the weak interface symbol
is removed by -Wl,-dead_strip.

Reviewers: kcc, compnerd, aaron.ballman

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37636

llvm-svn: 312914
2017-09-11 13:50:39 +00:00
Sanjay Patel
7c5563dc55 [InstSimplify] reorder methods; NFC
I'm trying to refactor some shared code for integer div/rem,
but I keep having to scroll through fdiv. The FP ops have
nothing in common with the integer ops, so I'm moving FP
below everything else. 

While here, improve a couple of comments and fix some formatting.

llvm-svn: 312913
2017-09-11 13:34:27 +00:00
Simon Pilgrim
1c377beb13 [X86][SSE] Add further test cases showing failure to compute sign bits through PACKSS
Suggested in D37680

Note: had to drop AVX512VL tests as there is an infinite loop in the new tests that needs further investigation (not relevant to D37680).
llvm-svn: 312910
2017-09-11 12:18:43 +00:00
Gadi Haber
624f0afbec [X86][SKX][KNL] Updating several CodeGen tests to use the attr flag instead of mcpu flag
NFC.
 Updated 3 Codegen regression tests to use the -mattr flag instead of the -mcpu flags as follows:
 Instead of -mcpu=skx use -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq
 Instead of -mcpu=knl use -mattr=+avx512f

Reviewers: delena
Revision: https://reviews.llvm.org/D37674
llvm-svn: 312909
2017-09-11 11:26:20 +00:00
Andre Vieira
ff00b0b024 [ARM] Enable the use of SVC anywhere in an IT block
Differential Revision: https://reviews.llvm.org/D37374

llvm-svn: 312908
2017-09-11 11:11:17 +00:00
Michael Zuckerman
3fa3db9a29 [Interleved][Stride 3]Adding test for case the VF=64 target with AVX512.
llvm-svn: 312907
2017-09-11 10:57:15 +00:00
Simon Pilgrim
747571ec61 [X86][SSE] Add test showing failure to compute sign bits through PACKSS
Prevents combineLogicBlendIntoPBLENDV from merging to PBLENDV

llvm-svn: 312906
2017-09-11 10:50:03 +00:00
Dylan McKay
880b08eb60 [AVR] Enable the '__do_copy_data' function
Also enables '__do_clear_bss'.

These functions are automaticalled called by the CRT if they are
declared.

We need these to be called otherwise RAM will start completely
uninitialised, even though we need to copy RAM variables from progmem to
RAM.

llvm-svn: 312905
2017-09-11 10:32:51 +00:00
Igor Breger
3f42dd4a6f [GlobalISel][X86] G_ANYEXT support.
Summary: G_ANYEXT support

Reviewers: zvi, delena

Reviewed By: delena

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D37675

llvm-svn: 312903
2017-09-11 09:41:13 +00:00
Ilya Biryukov
e859710b65 Fixed a typo in llvm-cov/deferred-region.cpp test.
Input redirection was using `2&>1` instead of `2>&1`.

llvm-svn: 312902
2017-09-11 09:22:44 +00:00
Tim Renouf
a63255f185 AMDGPU: trivial comment change
... to check commit access for new committer.

llvm-svn: 312900
2017-09-11 08:31:32 +00:00
Roger Ferrer Ibanez
c0927a36c4 [ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515 and also is being recommitted as its
first version caused PR34045.

This change:
 - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
 - lowering is done by first converting the boolean value into the carry flag
   using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
   using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
   operations does the actual addition.
 - for subtraction, given that ISD::SUBCARRY second result is actually a
   borrow, we need to invert the value of the second operand and result before
   and after using ARMISD::SUBE. We need to invert the carry result of
   ARMISD::SUBE to preserve the semantics.
 - given that the generic combiner may lower ISD::ADDCARRY and
   ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
   as well otherwise i64 operations now would require branches. This implies
   updating the corresponding test for unsigned.
 - add new combiner to remove the redundant conversions from/to carry flags
   to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
 - fixes PR34045

Differential Revision: https://reviews.llvm.org/D35192

llvm-svn: 312898
2017-09-11 07:38:05 +00:00
Elena Demikhovsky
9d38d8a38f Fixed a bug in splitting Scatter operation in the Type Legalizer.
After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken.
I'm chaining 2 nodes to prevent reordering.

Differential Revision https://reviews.llvm.org/D37670

llvm-svn: 312894
2017-09-11 06:18:15 +00:00
Lang Hames
7a884dd8d2 [ORC] Kill off a dead typedef.
llvm-svn: 312893
2017-09-11 01:09:46 +00:00
Simon Pilgrim
0c15bfe09a Use llvm_unreachable for unknown TargetCostKind.
TargetTransformInfo::getInstructionCost's switch covers all TargetCostKind cases so we shouldn't return for a default case.

llvm-svn: 312888
2017-09-10 18:42:23 +00:00
Simon Pilgrim
7c4f3f69df [X86][SSE] Tidyup + clang-format combineX86ShuffleChain call. NFCI.
llvm-svn: 312887
2017-09-10 18:18:45 +00:00
Simon Pilgrim
45250fa319 [X86][SSE] Move combineTo call out of combineX86ShufflesConstants. NFCI.
Move towards making it possible to use the shuffle combines for cases where we don't want to call DCI.CombineTo() with the result.

llvm-svn: 312886
2017-09-10 18:10:49 +00:00
Sanjay Patel
1a5f2e958a [InstSimplify] refactor udiv/urem code and add tests; NFCI
This removes some duplicated code and makes it easier to support signed div/rem
in a similar way if we want to do that. Note that the existing comments were not
accurate - we don't need a constant divisor to simplify; icmp simplification does
more than that. But as the added tests show, it could go even further.

llvm-svn: 312885
2017-09-10 17:55:08 +00:00
Simon Pilgrim
add6eb986b [X86][SSE] Move combineTo call out of combineX86ShuffleChain. NFCI.
First step towards making it possible to use the shuffle combines for cases where we don't want to call DCI.CombineTo() with the result.

llvm-svn: 312884
2017-09-10 14:06:41 +00:00
Elena Demikhovsky
d4e9778453 Added a test that demonstrates a ug in Scatter scheduling.
The bug is going to be fixed in an upcomming patch.
 

llvm-svn: 312883
2017-09-10 13:20:42 +00:00
Coby Tayree
c27f451050 [X86][X86AsmParser] adding const on InlineAsmIdentifierInfo in CreateMemForInlineAsm. NFC.
llvm-svn: 312881
2017-09-10 12:21:24 +00:00
Uriel Korach
b8b7209ffa Revert "adding autoUpgrade support to broadcast[f|i]32x2 intrinsics"
This reverts commit r312879 - An accidental partial commit.

llvm-svn: 312880
2017-09-10 09:07:21 +00:00
Uriel Korach
34f7febfe4 adding autoUpgrade support to broadcast[f|i]32x2 intrinsics
llvm-svn: 312879
2017-09-10 08:40:13 +00:00
Uriel Korach
32b30a50d0 Test commit
llvm-svn: 312878
2017-09-10 08:31:22 +00:00
Sanjoy Das
6a1155666e [SCEV] Re-arrange public and private sections to be contiguous; NFC
llvm-svn: 312876
2017-09-10 03:54:22 +00:00
Simon Pilgrim
513c04652e [X86] Add v2i4 store test case (PR20012)
llvm-svn: 312874
2017-09-09 20:28:50 +00:00
Simon Pilgrim
a3d5f0e106 [X86] Add v2i2 test case (PR20011)
llvm-svn: 312873
2017-09-09 20:22:35 +00:00
Simon Pilgrim
ef30f9b210 [X86][FMA] Regenerate FMA tests
llvm-svn: 312871
2017-09-09 19:25:59 +00:00
Nuno Lopes
4e212e275d Merge isKnownNonNull into isKnownNonZero
It now knows the tricks of both functions.
Also, fix a bug that considered allocas of non-zero address space to be always non null

Differential Revision: https://reviews.llvm.org/D37628

llvm-svn: 312869
2017-09-09 18:23:11 +00:00
Simon Pilgrim
2e5d8e7266 [X86][SSE] i32 vector multiplications test cases from PR6399
llvm-svn: 312868
2017-09-09 18:18:17 +00:00
Simon Pilgrim
42df0a6b95 [X86][MOVBE] Fix typo in MOVBE scheduling test names
Copy+paste is not your friend

llvm-svn: 312867
2017-09-09 17:52:44 +00:00
Craig Topper
d87f426279 [X86] Don't disable slow INC/DEC if optimizing for size
Summary:
Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size.

This appears to match gcc behavior.

Reviewers: chandlerc, zvi, RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37177

llvm-svn: 312866
2017-09-09 17:11:59 +00:00
MinSeong Kim
6b3d855c39 [CMake] Update GetSVN.cmake to handle repo
Summary:
When repo is used with git, 'clang --version' option does not display
the correct revision information (i.e. git hash on TOP) as the following:

clang version 6.0.0 --->
clang version 6.0.0 (clang version) (llvm version)

This is because repo also creates .git/svn folder as git-svn does and
this makes repo with git uses "git svn info" command, which is only for
git-svn, to retrieve its revision information, making null for the info.
To correctly distinguish between git-svn and repo with git, the folder
hierarchy to specify for git-svn should be .git/svn/refs as the "git svn
info" command depends on the revision data in .git/svn/refs. This patch
in turn makes repo with git passes through to the third macro,
get_source_info_git, in  get_source_info function, resulting in correctly
retrieving the revision information for repo with git using "git log ..."
command.

This patch is tested with git, svn, git-svn, and repo with git.

Reviewers: llvm-commits, probinson, rnk

Reviewed By: rnk

Subscribers: rnk, mehdi_amini, beanz, mgorny

Differential Revision: https://reviews.llvm.org/D35532

llvm-svn: 312864
2017-09-09 14:17:52 +00:00
Sanjay Patel
fa64325142 [DivRemPairs] split tests per target to account for bots that don't build for all targets
llvm-svn: 312863
2017-09-09 14:10:59 +00:00
Sanjay Patel
554ba948c2 [DivRempairs] add a pass to optimize div/rem pairs (PR31028)
This is intended to be a superset of the functionality from D31037 (EarlyCSE) but implemented 
as an independent pass, so there's no stretching of scope and feature creep for an existing pass. 
I also proposed a weaker version of this for SimplifyCFG in D30910. And I initially had almost 
this same functionality as an addition to CGP in the motivating example of PR31028:
https://bugs.llvm.org/show_bug.cgi?id=31028

The advantage of positioning this ahead of SimplifyCFG in the pass pipeline is that it can allow 
more flattening. But it needs to be after passes (InstCombine) that could sink a div/rem and
undo the hoisting that is done here.

Decomposing remainder may allow removing some code from the backend (PPC and possibly others).

Differential Revision: https://reviews.llvm.org/D37121 

llvm-svn: 312862
2017-09-09 13:38:18 +00:00
NAKAMURA Takumi
a236420560 CoverageMappingTest.cpp: Suppress warnings. [-Wdocumentation]
llvm-svn: 312861
2017-09-09 06:19:53 +00:00
Craig Topper
100b9ea58d [X86] Call removeDeadNode when we're done doing custom isel for mul, div and test
Summary:
Once we've done our custom isel for these nodes, I think we should be calling removeDeadNode to prune them out of the DAG. Table driven isel ultimately either calls morphNodeTo which modifies a node and doesn't leave dead nodes. Or it emits new nodes and then calls removeDeadNode as part of Opc_CompleteMatch.

If you run a simple multiply test case like this through llc with -debug you'll see a umul_lohi node get printed as part of the dump for Instruction Selection ends.

```
define i64 @foo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
  %conv = zext i64 %a to i128
  %conv1 = zext i64 %b to i128
  %mul = mul nuw nsw i128 %conv1, %conv
  %shr = lshr i128 %mul, 64
  %conv2 = trunc i128 %shr to i64
  ret i64 %conv2
}
```

Reviewers: RKSimon, spatel, zvi, guyblank, niravd

Reviewed By: niravd

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37547

llvm-svn: 312857
2017-09-09 05:57:20 +00:00
Craig Topper
8816811ac5 [X86] Use ReplaceNode instead of ReplaceUses when converting X86ISD::SHRUNKBLEND to ISD::VSELECT during isel.
This ensures that the SHRUNKBLEND node gets erased immediately.

llvm-svn: 312856
2017-09-09 05:57:19 +00:00