7 Commits

Author	SHA1	Message	Date
Evan Cheng	7624839811	PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff ... the bits being cleared by the AND are not demanded by the BFI. The previous BFI dag combine rule was actually incorrect (or used to be correct until BFI representation changed). rdar://9609030 llvm-svn: 133034	2011-06-15 01:12:31 +00:00
Jakob Stoklund Olesen	4755a27704	Fix a bunch of ARM tests to be register allocation independent. ... llvm-svn: 130800	2011-05-03 22:31:21 +00:00
Evan Cheng	6a2bed92f5	bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 ... llvm-svn: 121746	2010-12-14 03:22:07 +00:00
Evan Cheng	b6773d7e1f	(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 ... llvm-svn: 121606	2010-12-11 04:11:38 +00:00
Jim Grosbach	d2cf0742a4	Update tests to handle MC-inst instruction printing of shift operations. The ... legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. llvm-svn: 114221	2010-09-17 21:58:46 +00:00
Jim Grosbach	270540da7b	Add combiner patterns to more effectively utilize the BFI (bitfield insert) ... instruction for non-constant operands. This includes the case referenced in the README.txt regarding a bitfield copy. llvm-svn: 108608	2010-07-17 03:30:54 +00:00
Jim Grosbach	749f4fca0a	Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction ... and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. llvm-svn: 108570	2010-07-16 23:05:05 +00:00