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34cb8f3e4d
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42 Commits

Author SHA1 Message Date
Daniel Sanders
34cb8f3e4d [mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) 
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
  operation and implemented the DAG combines necessary to fold sign/zero
  extends into the extract.

llvm-svn: 191199
 2013-09-23 14:03:12 +00:00
Daniel Sanders
d1df1263eb [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics) 
llvm-svn: 191198
 2013-09-23 13:40:21 +00:00
Daniel Sanders
7d945d142d [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) 
llvm-svn: 191195
 2013-09-23 13:22:24 +00:00
Daniel Sanders
91c78d1d33 [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) 
llvm-svn: 191194
 2013-09-23 12:57:42 +00:00
Daniel Sanders
d3c403c386 [mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) 
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
    This is a special case of BUILD_VECTOR that covers the case the
    BUILD_VECTOR is a splat operation.
* Added VSPLATD
    This is a special case of VSPLAT that handles the cases when v2i64 is legal

llvm-svn: 191191
 2013-09-23 12:02:46 +00:00
Daniel Sanders
e3f2e5de18 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics) 
llvm-svn: 190518
 2013-09-11 11:58:30 +00:00
Daniel Sanders
96466ff8b4 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics) 
llvm-svn: 190512
 2013-09-11 10:51:30 +00:00
Daniel Sanders
a52c7f09dc [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics) 
llvm-svn: 190509
 2013-09-11 10:38:58 +00:00
Daniel Sanders
f68b00e629 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics) 
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.

llvm-svn: 190507
 2013-09-11 10:28:16 +00:00
Daniel Sanders
534d28aa11 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics 
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
 2013-09-11 09:59:17 +00:00
Daniel Sanders
32227b7995 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b) 
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
 2013-09-10 09:51:43 +00:00
Akira Hatanaka
c11e303acd [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.

llvm-svn: 190226
 2013-09-07 00:02:02 +00:00
Daniel Sanders
10a7da8f65 [mips][msa] Indentation 
llvm-svn: 190156
 2013-09-06 13:25:06 +00:00
Daniel Sanders
11008ea159 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance 
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
 2013-09-06 13:15:05 +00:00
Daniel Sanders
22d0137a75 [mips][msa] Made the operand register sets optional for the VEC formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
 2013-09-06 13:01:47 +00:00
Daniel Sanders
0eb9e53280 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
 2013-09-06 12:50:52 +00:00
Daniel Sanders
cb68899283 [mips][msa] Made the operand register sets optional for the 3RF_4RF format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
 2013-09-06 12:44:13 +00:00
Daniel Sanders
d9577fe859 [mips][msa] Made the operand register sets optional for the 3RF formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
 2013-09-06 12:32:57 +00:00
Daniel Sanders
6089833291 [mips][msa] Made the operand register sets optional for the 3R_4R format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
 2013-09-06 12:30:43 +00:00
Daniel Sanders
e8f95344a5 [mips][msa] Made the operand register sets optional for the 2RF format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
 2013-09-06 12:28:13 +00:00
Daniel Sanders
5e6aa9c0b4 [mips][msa] Made the operand register sets optional for the I8 format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
 2013-09-06 12:25:47 +00:00
Daniel Sanders
caabc263f0 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
 2013-09-06 12:23:19 +00:00
Daniel Sanders
e90f0ba299 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
 2013-09-06 12:10:24 +00:00
Daniel Sanders
66131ccd3e [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size 
No functional change

llvm-svn: 190134
 2013-09-06 11:01:38 +00:00
Daniel Sanders
d571ce1dd4 [mips][msa] Made the operand register sets optional for the 3R format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133
 2013-09-06 10:59:24 +00:00
Daniel Sanders
87992178d5 [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. 
No functional change

llvm-svn: 190131
 2013-09-06 10:55:15 +00:00
Daniel Sanders
7d6b0c31fc [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v 
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.

llvm-svn: 189478
 2013-08-28 12:14:50 +00:00
Daniel Sanders
86a3b104b1 [mips][msa] Added load/store intrinsics. 
llvm-svn: 189476
 2013-08-28 12:04:29 +00:00
Daniel Sanders
6583601738 [mips][msa] Added move.v 
llvm-svn: 189471
 2013-08-28 10:44:47 +00:00
Daniel Sanders
21800e80c1 [mips][msa] Added cfcmsa, and ctcmsa 
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.

llvm-svn: 189468
 2013-08-28 10:26:24 +00:00
Daniel Sanders
3740f20366 [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri 
llvm-svn: 189467
 2013-08-28 10:12:09 +00:00
Daniel Sanders
b2c1c16a0a [mips][msa] Added bitconverts for vector types for big and little-endian 
llvm-svn: 189330
 2013-08-27 09:40:30 +00:00
Daniel Sanders
c6286de5e8 [mips][msa] Split MSA128 regset into size-specific sets containing the same registers. 
llvm-svn: 189095
 2013-08-23 10:10:13 +00:00
Daniel Sanders
30561c36b8 [mips][msa] Removed fcge, fcgt, fsge, fsgt 
These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782
 2013-08-20 09:41:47 +00:00
Daniel Sanders
91c40d80de [mips][msa] Added insve 
llvm-svn: 188777
 2013-08-20 09:22:54 +00:00
Daniel Sanders
15341e9a12 [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v 
llvm-svn: 188767
 2013-08-20 08:38:21 +00:00
Daniel Sanders
ee0e14ab3f Reverted test commit (r188556) 
llvm-svn: 188557
 2013-08-16 15:27:12 +00:00
Daniel Sanders
aac10b8a53 Test commit. Just a blank line 
llvm-svn: 188556
 2013-08-16 15:26:36 +00:00
Jack Carter
2c2f78cead [Mips][msa] Added the simple builtins (madd_q to xori) 
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori

Patch by Daniel Sanders

llvm-svn: 188460
 2013-08-15 14:22:07 +00:00
Jack Carter
8798c3bae2 [Mips][msa] Added the simple builtins (fadd to ftq) 
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders

llvm-svn: 188458
 2013-08-15 13:45:36 +00:00
Jack Carter
80890657b3 [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) 
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders

llvm-svn: 188457
 2013-08-15 12:24:57 +00:00
Jack Carter
da7e928e92 [Mips][msa] Added initial MSA support. 
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
 2013-08-13 20:54:07 +00:00