1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 06:22:56 +02:00
Commit Graph

17841 Commits

Author SHA1 Message Date
Reid Spencer
34f69893be Add and Operator== method to ValID so equality can be done properly for
named or numbered ValIDs.

llvm-svn: 35172
2007-03-19 18:34:28 +00:00
Reid Spencer
135ca5e8c4 For PR1258:
Radically simplify the SlotMachine. There is no need to keep Value planes
around any more. This change causes slot numbering to number all un-named,
non-void values starting at 0 and incrementing monotonically through the
function, regardless of type (including BasicBlocks). Getting slot numbers
is now a single lookup operation instead of a double lookup.

llvm-svn: 35171
2007-03-19 18:32:53 +00:00
Chris Lattner
5f1d3ac7e4 fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll
llvm-svn: 35169
2007-03-19 18:25:57 +00:00
Evan Cheng
822f7b5213 Remove -reduce-joining-phys-regs options. Make it on by default.
llvm-svn: 35165
2007-03-19 18:08:26 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies.
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable.
llvm-svn: 35161
2007-03-19 07:09:02 +00:00
Evan Cheng
498f19548c Added isReMaterializable.
llvm-svn: 35160
2007-03-19 06:22:07 +00:00
Evan Cheng
3b690ab936 Minor bug fix.
llvm-svn: 35153
2007-03-19 04:22:35 +00:00
Chris Lattner
59fe2be1c4 fix a warning
llvm-svn: 35152
2007-03-19 00:39:32 +00:00
Chris Lattner
5e2e3ddb7e implement the next chunk of SROA with memset/memcpy's of aggregates. This
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

llvm-svn: 35150
2007-03-19 00:16:43 +00:00
Nick Lewycky
2a51ea0c0e Clean up this code and fix subtract miscompile.
llvm-svn: 35146
2007-03-18 22:58:46 +00:00
Chris Lattner
adf7003452 Implement InstCombine/and-xor-merge.ll:test[12].
Rearrange some code to simplify it now that shifts are binops

llvm-svn: 35145
2007-03-18 22:51:34 +00:00
Chris Lattner
a1df6908d2 minor updates
llvm-svn: 35143
2007-03-18 22:41:33 +00:00
Nick Lewycky
04ecc07c25 This is implemented. We now generate:
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
2007-03-18 14:37:20 +00:00
Evan Cheng
b4713633aa - Merge UsedBlocks info after two virtual registers are coalesced.
- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141
2007-03-18 09:05:55 +00:00
Evan Cheng
76df6abc61 Keep UsedBlocks info accurate.
llvm-svn: 35140
2007-03-18 09:02:31 +00:00
Nick Lewycky
41f13d431a Propagate ValueRanges across equality.
Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

llvm-svn: 35138
2007-03-18 01:09:32 +00:00
Anton Korobeynikov
b34e09291b Silence warning
llvm-svn: 35137
2007-03-17 14:48:06 +00:00
Evan Cheng
5be8544e8a Track the BB's where each virtual register is used.
llvm-svn: 35135
2007-03-17 09:29:54 +00:00
Evan Cheng
ca1e6eea8e Joining a live interval of a physical register with a virtual one can turn out
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134
2007-03-17 09:27:35 +00:00
Evan Cheng
65d69fe08d Use SmallSet instead of std::set.
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
Evan Cheng
8552300ab1 If sdisel has decided to sink GEP index expression into any BB. Replace all uses
in that BB.

llvm-svn: 35132
2007-03-17 08:22:49 +00:00
Devang Patel
2dabb16eac Support 'I' inline asm constraint.
llvm-svn: 35129
2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio
f756184c5e Only ARMv6 has BSWAP.
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
2007-03-16 22:54:16 +00:00
Evan Cheng
77099bef05 Turn on GEP index sinking by default.
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
Evan Cheng
449900b988 Stupid bug.
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
Bill Wendling
8ced23ee5a And now support for MMX logical operations.
llvm-svn: 35125
2007-03-16 09:44:46 +00:00
Evan Cheng
c3e7d4b884 Sink a binary expression into its use blocks if it is a loop invariant
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
2007-03-16 08:46:27 +00:00
Evan Cheng
4858c6f781 Added isLegalAddressExpression(). Only allows X +/- C for now.
llvm-svn: 35122
2007-03-16 08:43:56 +00:00
Evan Cheng
ce8b779c6c Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.

llvm-svn: 35121
2007-03-16 08:42:32 +00:00
Nick Lewycky
de44438e24 Add more comments and update to new asm syntax.
Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119
2007-03-16 02:37:39 +00:00
Bill Wendling
feaff80149 Multiplication support for MMX.
llvm-svn: 35118
2007-03-15 21:24:36 +00:00
Evan Cheng
ab9145d617 Debugging output stuff.
llvm-svn: 35117
2007-03-15 21:19:28 +00:00
Evan Cheng
dc6ba035bc Estimate a cost using the possible number of scratch registers required and use
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109
2007-03-14 22:43:40 +00:00
Evan Cheng
00edaa08b5 Under X86-64 large code model, do not emit 32-bit pc relative calls.
llvm-svn: 35108
2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712 Notes about codegen issues.
llvm-svn: 35107
2007-03-14 21:03:53 +00:00
Evan Cheng
50a0af3b57 Clean up.
llvm-svn: 35105
2007-03-14 20:20:19 +00:00
Evan Cheng
2617c8dd3a Oops.
llvm-svn: 35104
2007-03-14 19:44:58 +00:00
Evan Cheng
371b8e8fa9 X86-64 JIT is in large code model. Need stubs for direct calls.
llvm-svn: 35097
2007-03-14 10:51:55 +00:00
Evan Cheng
1092e481ce x86-64 JIT stub codegen.
llvm-svn: 35096
2007-03-14 10:48:08 +00:00
Evan Cheng
15de6714a4 Preliminary support for X86-64 JIT stub codegen.
llvm-svn: 35095
2007-03-14 10:44:30 +00:00
Zhou Sheng
5c6399dab7 ShiftAmt might equal to zero. Handle this situation.
llvm-svn: 35094
2007-03-14 09:07:33 +00:00
Zhou Sheng
4415c2647e Enable KnownZero/One.clear().
llvm-svn: 35093
2007-03-14 03:21:24 +00:00
Evan Cheng
399f56eac2 Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089
2007-03-13 23:25:11 +00:00
Evan Cheng
7cbde8351a AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
Evan Cheng
7b24b3e474 Zero is always a legal AM immediate.
llvm-svn: 35087
2007-03-13 20:37:59 +00:00
Evan Cheng
bd964bd8eb Correct type info for isLegalAddressImmediate() check.
llvm-svn: 35086
2007-03-13 20:34:37 +00:00
Nicolas Geoffray
9c77df75ea Stack and register alignment of call arguments in the ELF ABI
llvm-svn: 35083
2007-03-13 15:02:46 +00:00
Chris Lattner
efc2339bd7 ifdef out some dead code.
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082
2007-03-13 14:27:42 +00:00