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Commit Graph

17596 Commits

Author SHA1 Message Date
Tim Northover
3556e52a02 Fix physical register liveness calculations:
+ Take account of clobbers
+ Give outputs priority over inputs since they happen later.

llvm-svn: 168360
2012-11-20 09:56:11 +00:00
Elena Demikhovsky
9f52a3ef84 Intel OCL built-ins calling conventions now support MacOS 32-bit.
llvm-svn: 168359
2012-11-20 09:37:57 +00:00
Simon Atanasyan
946ee234f3 Marking remote mcjit tests as XFAIL for MIPS.
llvm-svn: 168357
2012-11-20 07:25:17 +00:00
Chandler Carruth
47187cb94a Rework the rewriting of loads and stores for vector and integer allocas
to properly handle the combinations of these with split integer loads
and stores. This essentially replaces Evan's r168227 by refactoring the
code in a different way, and trynig to mirror that refactoring in both
the load and store sides of the rewriting.

Generally speaking there was some really problematic duplicated code
here that led to poorly founded assumptions and then subtle bugs. Now
much of the code actually flows through and follows a more consistent
style and logical path. There is still a tiny bit of duplication on the
store side of things, but it is much less bad.

This also changes the logic to never re-use a load or store instruction
as that was simply too error prone in practice.

I've added a few tests (one a reduction of the one in Evan's original
patch, which happened to be the same as the report in PR14349). I'm
going to look at adding a few more tests for things I found and fixed in
passing (such as the volatile tests in the vectorizable predicate).

This patch has survived bootstrap, and modulo one bugfix survived
Duncan's test suite, but let me know if anything else explodes.

llvm-svn: 168346
2012-11-20 01:12:50 +00:00
Anton Korobeynikov
7a285e97e2 Factor out type info emission into separate routine.
It turned out that ARM wants different layout of type infos.
This is yet another patch in attempt to fix PR7187 

llvm-svn: 168325
2012-11-19 21:06:26 +00:00
Jakob Stoklund Olesen
42930d7c54 Handle mixed normal and early-clobber defs on inline asm.
PR14376.

llvm-svn: 168320
2012-11-19 19:31:10 +00:00
Ulrich Weigand
c0920bb63a Enable MCJIT tests on PowerPC.
Disable old JIT tests on PowerPC.

llvm-svn: 168316
2012-11-19 17:57:07 +00:00
Duncan Sands
2d43cbfea0 Fix PR14060, an infinite loop in reassociate. The problem was that one of the
operands of the expression being written was wrongly thought to be reusable as
an inner node of the expression resulting in it turning up as both an inner node
*and* a leaf, creating a cycle in the def-use graph.  This would have caused the
verifier to blow up if things had gotten that far, however it managed to provoke
an infinite loop first.

llvm-svn: 168291
2012-11-18 19:27:01 +00:00
Andrew Trick
ab75b8798c Use a full triple for a PPC test case for asm syntax.
llvm-svn: 168283
2012-11-18 06:21:03 +00:00
NAKAMURA Takumi
5948e67968 MCJIT: [cygming] Give noop to __main also in RecordingMemoryManger. It is emitted in @main().
XFAIL(s) can be removed.

llvm-svn: 168282
2012-11-18 06:16:32 +00:00
NAKAMURA Takumi
0a04171e80 test/ExecutionEngine/MCJIT/stubs-remote.ll: Prune DOSish CRLF.
llvm-svn: 168281
2012-11-18 06:16:21 +00:00
Nick Lewycky
570e765264 Don't try to calculate the alignment of an unsigned type. Fixes PR14371!
llvm-svn: 168280
2012-11-18 05:39:39 +00:00
Andrew Trick
d4358df73b Silence the buildbots for this test while I figure out the triple
llvm-svn: 168249
2012-11-17 03:39:26 +00:00
Andrew Trick
52f84ce773 Broaden isSchedulingBoundary to check aliases of SP.
On PPC the stack pointer is X1, but ADJCALLSTACK writes R1.

Fixes PR14315: Register regmask dependency problem with misched.

llvm-svn: 168248
2012-11-17 03:35:11 +00:00
Hal Finkel
9dc292f3c5 Phi speculation improvement for BasicAA
This is a partial solution to PR14351. It removes some of the special
significance of the first incoming phi value in the phi aliasing checking logic
in BasicAA. In the context of a loop, the old logic assumes that the first
incoming value is the interesting one (meaning that it is the one that comes
from outside the loop), but this is often not the case.  With this change, we
now test first the incoming value that comes from a block other than the parent
of the phi being tested.

llvm-svn: 168245
2012-11-17 02:33:15 +00:00
Eli Friedman
d7496f6688 Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus.
llvm-svn: 168240
2012-11-17 01:52:46 +00:00
Chad Rosier
7aa7c0d952 [fast-isel] Add the -verify-machineinstrs to these test cases. The remaining
test cases require fixes to fast-isel before the verifier can be enabled.
Part of rdar://12594152

llvm-svn: 168233
2012-11-17 00:42:06 +00:00
Nadav Rotem
6ff38dc8d2 LoopVectorizer: Add initial support for pointer induction variables (for example: *dst++ = *src++).
At the moment we still require to have an integer induction variable (for example: i++).

llvm-svn: 168231
2012-11-17 00:27:03 +00:00
Akira Hatanaka
869eb1acb9 Initial implementation of MipsTargetLowering::isLegalAddressingMode.
llvm-svn: 168230
2012-11-17 00:25:41 +00:00
Evan Cheng
3fb5893b5d Teach SROA rewriteVectorizedStoreInst to handle cases when the loaded value is narrower than the stored value. rdar://12713675
llvm-svn: 168227
2012-11-17 00:05:06 +00:00
Andrew Kaylor
734b62b6ac Marking remote mcjit tests as XFAIL for cygwin (hopefully only temporarily).
llvm-svn: 168226
2012-11-17 00:02:50 +00:00
Andrew Kaylor
f132e42fe6 Marking remote mcjit tests as XFAIL for mingw32 (hopefully only temporarily).
llvm-svn: 168221
2012-11-16 23:38:16 +00:00
Andrew Kaylor
47462d3fe5 Marking remote mcjit tests as XFAIL for ARM (hopefully only temporarily).
llvm-svn: 168210
2012-11-16 22:21:04 +00:00
Weiming Zhao
85dce59506 Remove hard coded registers in ARM ldrexd and strexd instructions
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.

llvm-svn: 168207
2012-11-16 21:55:34 +00:00
Anton Korobeynikov
3cd85d754d Make sure FABS on v2f32 and v4f32 is legal on ARM NEON
This fixes PR14359

llvm-svn: 168200
2012-11-16 21:15:20 +00:00
Richard Osborne
c8f73df738 Fix handling of aliases to functions.
An alias to a function should use pc relative addressing.

llvm-svn: 168199
2012-11-16 21:12:38 +00:00
Justin Holewinski
a794462d5b [NVPTX] Order global variables in def-use order before emiting them in the final assembly
llvm-svn: 168198
2012-11-16 21:03:51 +00:00
Justin Holewinski
cef6246d31 Preserve address space of forward-referenced global variables in the LL parser
Before, the parser would assert on the following code:

@a2 = global i8 addrspace(1)* @a
@a = addrspace(1) global i8 0

because the type of @a was "i8*" instead of "i8 addrspace(1)*" when parsing
the initializer for @a2.

llvm-svn: 168197
2012-11-16 21:03:47 +00:00
Hemant Kulkarni
4fbbfcc6a6 Added program header emission
llvm-svn: 168195
2012-11-16 20:51:32 +00:00
Duncan Sands
33a1bb1041 InstructionSimplify should be able to simplify A+B==B+A to 'true'
but wasn't due to the same logic bug that caused PR14361.

llvm-svn: 168186
2012-11-16 19:41:26 +00:00
Duncan Sands
86ca3afe2e Fix PR14361: wrong simplification of A+B==B+A. You may think that the old logic
replaced by this patch is equivalent to the new logic, but you'd be wrong, and
that's exactly where the bug was.  There's a similar bug in instsimplify which
manifests itself as instsimplify failing to simplify this, rather than doing it
wrong, see next commit.

llvm-svn: 168181
2012-11-16 18:55:49 +00:00
Andrew Kaylor
3b722976b8 Adding new tests to test lli's pseudo-remote feature (-remote-mcjit).
llvm-svn: 168180
2012-11-16 18:51:59 +00:00
NAKAMURA Takumi
6c26c8f4b6 llvm/test/CodeGen/X86/hipe-cc*.ll: Add explicit -mcpu, or they don't expect to pass on Atom.
llvm-svn: 168171
2012-11-16 16:07:37 +00:00
Duncan Sands
98b6a4f4b5 Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.
llvm-svn: 168166
2012-11-16 12:36:39 +00:00
Amara Emerson
6ad9fb1a92 Add MCJIT test case for running global constructors.
llvm-svn: 168149
2012-11-16 11:17:00 +00:00
Hans Wennborg
220b5e3636 Constant::IsThreadDependent(): Use dyn_cast<Constant> instead of cast
It turns out that the operands of a Constant are not always themselves
Constant. For example, one of the operands of BlockAddress is
BasicBlock, which is not a Constant.

This should fix the dragonegg-x86_64-linux-gcc-4.6-test build which
broke in r168037.

llvm-svn: 168147
2012-11-16 10:33:25 +00:00
Craig Topper
ad33f996a6 Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types.
llvm-svn: 168141
2012-11-16 06:37:56 +00:00
Akira Hatanaka
ba0e266eb2 [mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot.

llvm-svn: 168131
2012-11-16 02:39:34 +00:00
Eli Bendersky
b6e1193a2e Add some tests for the FileCheck utility.
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/156007.html

llvm-svn: 168113
2012-11-15 23:42:51 +00:00
Eli Friedman
79932a2f77 Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
case to vector legalization so this actually works.

Patch by Pete Couperus.  Fixes PR12540.

llvm-svn: 168107
2012-11-15 22:44:27 +00:00
Adhemerval Zanella
c159b16933 PowerPC: Lowering floor intrinsic for Altivec
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.

llvm-svn: 168086
2012-11-15 20:56:03 +00:00
Hans Wennborg
73c4bb7fcb Make GlobalOpt be conservative with TLS variables (PR14309)
For global variables that get the same value stored into them
everywhere, GlobalOpt will replace them with a constant. The problem is
that a thread-local GlobalVariable looks like one value (the address of
the TLS var), but is different between threads.

This patch introduces Constant::isThreadDependent() which returns true
for thread-local variables and constants which depend on them (e.g. a GEP
into a thread-local array), and teaches GlobalOpt not to track such
values.

llvm-svn: 168037
2012-11-15 11:40:00 +00:00
Duncan Sands
f05d8752a2 Fix a crash observed by Shuxin Yang. The issue here is that LinearizeExprTree,
the utility for extracting a chain of operations from the IR, thought that it
might as well combine any constants it came across (rather than just returning
them along with everything else).  On the other hand, the factorization code
would like to see the individual constants (this is quite reasonable: it is
much easier to pull a factor of 3 out of 2*3 than it is to pull it out of 6;
you may think 6/3 isn't so hard, but due to overflow it's not as easy to undo
multiplications of constants as it may at first appear).  This patch therefore
makes LinearizeExprTree stupider: it now leaves optimizing to the optimization
part of reassociate, and sticks to just analysing the IR.

llvm-svn: 168035
2012-11-15 09:58:38 +00:00
Bill Schmidt
f294eb980a This patch is in preparation for adding medium code model support to the
PPC64 target.  The five tests modified herein test code generation that is
sensitive to the code model selected.  So I've added -code-model=small to
the RUN commands for each.

Since small code model is the default, this has no effect for now; but this
prepares us for eventually changing the default to medium code model for PPC64.

Test changes verified with small and medium code model as default on
powerpc64-unknown-linux-gnu.  All tests continue to pass.

llvm-svn: 167999
2012-11-14 23:23:27 +00:00
Jakub Staszak
8c20275ebf Make sure to not get AVX code on an AVX-capable host. Revealed in r167967.
llvm-svn: 167989
2012-11-14 22:24:01 +00:00
NAKAMURA Takumi
8adf86a12e test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the failure on i686 hosts.
llvm-svn: 167988
2012-11-14 22:22:37 +00:00
Eric Christopher
caf5a23d81 Remove the CellSPU port.
Approved by Chris Lattner.

llvm-svn: 167984
2012-11-14 22:09:20 +00:00
NAKAMURA Takumi
e40f4623cd llvm/test/CodeGen/X86/memset.ll: FileCheck-ize, and add another case on +avx.
llvm-svn: 167975
2012-11-14 21:01:40 +00:00
Jyotsna Verma
a472ef54f3 Added multiclass for post-increment load instructions.
llvm-svn: 167974
2012-11-14 20:38:48 +00:00
Benjamin Kramer
27983167e3 Force CPU in test so we don't accidentally get AVX code on an AVX-capable host.
llvm-svn: 167973
2012-11-14 20:31:42 +00:00