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Commit Graph

8483 Commits

Author SHA1 Message Date
Anton Korobeynikov
e48fe3dde8 Use StringSet instead of std::set<std::string>
llvm-svn: 52836
2008-06-27 21:22:49 +00:00
Anton Korobeynikov
eb63554d81 Provide correct encoding for PPC LWARX instructions.
Patch by Gary Benson!

llvm-svn: 52828
2008-06-27 16:10:20 +00:00
Owen Anderson
59ed35b2c2 Cache subregister relationships in a set in TargetRegisterInfo to allow faster lookups.
This speeds up LiveVariables from 0.6279s to 0.6165s on kimwitu++.

llvm-svn: 52818
2008-06-27 06:56:04 +00:00
Matthijs Kooijman
b1217bdbb0 Make LLVM compile on DragonFly BSD (PR2499).
Patch by Hasso Tepper!

llvm-svn: 52781
2008-06-26 10:36:58 +00:00
Dale Johannesen
f170e29cf5 Fixes the last x86-64 test failure in compat.exp:
<16 x float> is 64-byte aligned (for some reason),
which gets us into the stack realignment code.  The
computation changing FP-relative offsets to SP-relative
was broken, assiging a spill temp to a location
also used for parameter passing.  This
fixes it by rounding up the stack frame to a multiple
of the largest alignment (I concluded it wasn't fixable
without doing this, but I'm not very sure.)

llvm-svn: 52750
2008-06-26 01:51:13 +00:00
Evan Cheng
71fbfe73c1 - Fix a x86 vector isel bug: illegal transformation of a vector_shuffle into a
shift.
- Add a readme entry for a missing vector_shuffle optimization that results in
  awful codegen.

llvm-svn: 52740
2008-06-25 20:52:59 +00:00
Chris Lattner
ef1aa7c9db Switch the PPC backend and target-independent JIT to use the libsystem
InvalidateInstructionCache method instead of calling through
a hook on the JIT.  This is a host feature, not a target feature.

llvm-svn: 52734
2008-06-25 17:18:44 +00:00
Dan Gohman
8205b235b9 SimpleInstructionSelector is here no more.
llvm-svn: 52725
2008-06-25 16:38:59 +00:00
Dan Gohman
404964dbc0 Remove the OrigVT member from AtomicSDNode, as it is redundant with
the base SDNode's VTList.

llvm-svn: 52722
2008-06-25 16:07:49 +00:00
Mon P Wang
7d89d61387 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub

llvm-svn: 52706
2008-06-25 08:15:39 +00:00
Evan Cheng
bab5925a0b Enable two-address remat by default.
llvm-svn: 52701
2008-06-25 01:16:38 +00:00
Dale Johannesen
fdf8fe6c03 Add v2f32 (MMX) type to X86. Support is primitive:
load,store,call,return,bitcast.  This is enough to
make call and return work.

llvm-svn: 52691
2008-06-24 22:01:44 +00:00
Evan Cheng
a62f5f0f82 If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction.
llvm-svn: 52670
2008-06-24 07:10:51 +00:00
Dan Gohman
9941a2dab3 Add a note about a potential PIC optimization.
llvm-svn: 52663
2008-06-24 00:53:07 +00:00
Dan Gohman
ebc59c90b7 Fixes for being compiled PIC on Linux. This isn't the most
general solution possible, but it's a fairly simple one.
Based on a patch from the OpenGTL project!

llvm-svn: 52662
2008-06-24 00:50:01 +00:00
Dan Gohman
c1aa753f00 Remove unnecessary #includes.
llvm-svn: 52613
2008-06-22 19:21:26 +00:00
Dan Gohman
bed65a69c3 Use MachineBasicBlock::transferSuccessors.
llvm-svn: 52594
2008-06-21 20:21:19 +00:00
Eli Friedman
570aa6f801 Fix a bug with <8 x i16> shuffle lowering on X86 where parts of the
shuffle could be skipped.  The check is invalid because the loop index i 
doesn't correspond to the element actually inserted. The correct check is
already done a few lines earlier, for whether the element is already in 
the right spot, so this shouldn't have any effect on the codegen for 
code that was already correct.

llvm-svn: 52486
2008-06-19 06:09:51 +00:00
Evan Cheng
4416f16a6a Unneeded include's.
llvm-svn: 52478
2008-06-19 01:21:02 +00:00
Evan Cheng
0570953e28 XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are.
llvm-svn: 52454
2008-06-18 08:13:07 +00:00
Evan Cheng
deb754898b Unbreak DECLARE isel in pic mode.
llvm-svn: 52439
2008-06-18 02:48:27 +00:00
Anton Korobeynikov
6a779ad6fa Add one more 'magic' define :)
llvm-svn: 52420
2008-06-17 17:57:43 +00:00
Anton Korobeynikov
cdfbb1eae5 Unbreak non-PPC builds
llvm-svn: 52419
2008-06-17 17:38:31 +00:00
Anton Korobeynikov
5b04f6d658 Provide generic hooks for icache invalidation. Add PPC implementation.
Patch by Gary Benson!

llvm-svn: 52418
2008-06-17 17:30:05 +00:00
Evan Cheng
89e2e3292d Rather than avoiding to wrap ISD::DECLARE GV operand in X86ISD::Wrapper, simply handle it at dagisel time with x86 specific isel code.
llvm-svn: 52377
2008-06-17 02:01:22 +00:00
Evan Cheng
4e7b7b21a2 Horizontal-add instructions are not commutative.
llvm-svn: 52363
2008-06-16 21:16:24 +00:00
Evan Cheng
acd614c262 mpsadbw is commutable.
llvm-svn: 52352
2008-06-16 20:25:59 +00:00
Chris Lattner
ddfa0590ae Add support for icache invalidation on non-darwin ppc systems.
Patch by Gary Benson!

llvm-svn: 52332
2008-06-16 17:04:06 +00:00
Evan Cheng
2dfe8c2435 Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
llvm-svn: 52308
2008-06-16 07:33:11 +00:00
Chris Lattner
0b945db11c Switch from generating the int128 typedefs based on targetdata to generating
them based on the end-compiler's capabilities.  This fixes PR2453

llvm-svn: 52297
2008-06-16 04:25:29 +00:00
Andrew Lenharth
327c3e7559 add missing atomic intrinsic from gcc
llvm-svn: 52270
2008-06-14 05:48:15 +00:00
Duncan Sands
40c8db881a Disable some DAG combiner optimizations that may be
wrong for volatile loads and stores.  In fact this
is almost all of them!  There are three types of
problems: (1) it is wrong to change the width of
a volatile memory access.  These may be used to
do memory mapped i/o, in which case a load can have
an effect even if the result is not used.  Consider
loading an i32 but only using the lower 8 bits.  It
is wrong to change this into a load of an i8, because
you are no longer tickling the other three bytes.  It
is also unwise to make a load/store wider.  For
example, changing an i16 load into an i32 load is
wrong no matter how aligned things are, since the
fact of loading an additional 2 bytes can have
i/o side-effects.  (2) it is wrong to change the
number of volatile load/stores: they may be counted
by the hardware.  (3) it is wrong to change a volatile
load/store that requires one memory access into one
that requires several.  For example on x86-32, you
can store a double in one processor operation, but to
store an i64 requires two (two i32 stores).  In a
multi-threaded program you may want to bitcast an i64
to a double and store as a double because that will
occur atomically, and be indivisible to other threads.
So it would be wrong to convert the store-of-double
into a store of an i64, because this will become two
i32 stores - no longer atomic.  My policy here is
to say that the number of processor operations for
an illegal operation is undefined.  So it is alright
to change a store of an i64 (requires at least two
stores; but could be validly lowered to memcpy for
example) into a store of double (one processor op).
In short, if the new store is legal and has the same
size then I say that the transform is ok.  It would
also be possible to say that transforms are always
ok if before they were illegal, whether after they
are illegal or not, but that's more awkward to do
and I doubt it buys us anything much.
However this exposed an interesting thing - on x86-32
a store of i64 is considered legal!  That is because
operations are marked legal by default, regardless of
whether the type is legal or not.  In some ways this
is clever: before type legalization this means that
operations on illegal types are considered legal;
after type legalization there are no illegal types
so now operations are only legal if they really are.
But I consider this to be too cunning for mere mortals.
Better to do things explicitly by testing AfterLegalize.
So I have changed things so that operations with illegal
types are considered illegal - indeed they can never
map to a machine operation.  However this means that
the DAG combiner is more conservative because before
it was "accidentally" performing transforms where the
type was illegal because the operation was nonetheless
marked legal.  So in a few such places I added a check
on AfterLegalize, which I suppose was actually just
forgotten before.  This causes the DAG combiner to do
slightly more than it used to, which resulted in the X86
backend blowing up because it got a slightly surprising
node it wasn't expecting, so I tweaked it.

llvm-svn: 52254
2008-06-13 19:07:40 +00:00
Anton Korobeynikov
74422b3cd0 Properly lower DYNAMIC_STACKALLOC - bracket all black magic with
CALLSEQ_BEGIN & CALLSEQ_END.

llvm-svn: 52225
2008-06-11 20:16:42 +00:00
Dan Gohman
ce662293ed CPPBackend support for extractvalue and insertvalue.
llvm-svn: 52147
2008-06-09 14:12:10 +00:00
Dan Gohman
ee7b8797d0 Abort on an unrecognized opcode.
llvm-svn: 52146
2008-06-09 14:09:13 +00:00
Dan Gohman
5f7b94fd7b Update the CPP backend for the ConstantFP::get API change.
llvm-svn: 52144
2008-06-09 14:08:11 +00:00
Rafael Espindola
feaadb1e05 add support for PIC on linux x86-64
llvm-svn: 52139
2008-06-09 09:52:31 +00:00
Duncan Sands
fe2a970a5c Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.

llvm-svn: 52098
2008-06-08 20:54:56 +00:00
Bruno Cardoso Lopes
c91758a7fc Added FP instruction formats.
llvm-svn: 52086
2008-06-08 01:39:36 +00:00
Bill Wendling
346669b97f Temporarily reverting r52056. It's causing PPC to fail to bootstrap.
llvm-svn: 52085
2008-06-08 01:36:24 +00:00
Bruno Cardoso Lopes
b0cb678a47 Added support for FP Registers
llvm-svn: 52079
2008-06-07 21:32:41 +00:00
Evan Cheng
6b5b097805 Revert r52046. It broke cbe on x86 / Mac OS X.
llvm-svn: 52071
2008-06-07 07:50:29 +00:00
Evan Cheng
b19baf81ba Typo.
llvm-svn: 52062
2008-06-06 21:00:10 +00:00
Evan Cheng
3ac5c6575a PPC preferred loop alignment is 16.
llvm-svn: 52056
2008-06-06 19:50:46 +00:00
Anton Korobeynikov
8c40a176f7 Handle assembler identifiers specially in CBE. This fixes PR2418.
llvm-svn: 52046
2008-06-06 16:08:26 +00:00
Duncan Sands
d634afe3aa Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Bruno Cardoso Lopes
23e9cfc581 Added custom isel for MUL, SDIVREM, UDIVREM, SMUL_LOHI and UMUL_LOHI nodes
MUL is not anymore directly matched because its a pseudoinstruction.
LogicI class fixed to zero-extend immediates. 

llvm-svn: 52036
2008-06-06 06:37:31 +00:00
Bruno Cardoso Lopes
7b58f690cb Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC

llvm-svn: 52031
2008-06-06 00:58:26 +00:00
Evan Cheng
badbe3e3fa Don't break strict aliasing.
llvm-svn: 52026
2008-06-05 22:59:21 +00:00
Chris Lattner
7e3db1af97 Rewrite a bunch of the CBE's inline asm code, giving it the
ability to handle indirect input operands.  This fixes PR2407.

llvm-svn: 51952
2008-06-04 18:03:28 +00:00