1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 22:42:46 +02:00
Commit Graph

52236 Commits

Author SHA1 Message Date
Stepan Dyatkovskiy
38bc1a8899 Fixed comment in loop-unswitch.
llvm-svn: 148252
2012-01-16 20:48:04 +00:00
Jakob Stoklund Olesen
208476ccd0 Give better scavenger errors by invoking the verifier.
llvm-svn: 148251
2012-01-16 20:38:31 +00:00
Jakob Stoklund Olesen
77ce60119b Add a new kind of MachineOperand: MO_RegisterMask.
Register masks will be used as a compact representation of large clobber
lists.  Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers.  That's more than 1kB of useless
operands per call site.

A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered.  The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().

By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.

This patch introduces the new operand kind.  Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.

llvm-svn: 148250
2012-01-16 19:22:00 +00:00
Eli Friedman
a343d87eac Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
llvm-svn: 148240
2012-01-16 16:42:21 +00:00
Eli Friedman
a2b480b010 Get rid of unused codegen-only instruction.
llvm-svn: 148239
2012-01-16 16:29:35 +00:00
Craig Topper
d1f51dc860 Give priority to AVX over SSE for 128-bit floating point unpck instructions.
llvm-svn: 148233
2012-01-16 09:56:42 +00:00
Eli Bendersky
ed17ae8c86 A fix for the previous commit: "integer constant is too large for ‘long’ type" error on some 32-bit bots
llvm-svn: 148232
2012-01-16 09:31:10 +00:00
Eli Bendersky
973d44eb7c Adding a basic ELF dynamic loader and MC-JIT for ELF. Functionality is currently basic and will be enhanced with future patches.
Patch developed by Andy Kaylor and Daniel Malea. Reviewed on llvm-commits.

llvm-svn: 148231
2012-01-16 08:56:09 +00:00
David Blaikie
d828c91e69 Refactor variables unused under non-assert builds (& remove two entirely unused variables).
llvm-svn: 148230
2012-01-16 05:17:39 +00:00
Pete Cooper
a68251aaac Changed intrinsic ID operand to a target constant as its not used in any arithmetic so should not be checked in legalisation
llvm-svn: 148228
2012-01-16 04:08:12 +00:00
Nadav Rotem
b36c029e3b [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.

Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.

llvm-svn: 148225
2012-01-15 19:27:55 +00:00
Benjamin Kramer
14443a8cf6 Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
llvm-svn: 148218
2012-01-15 13:16:05 +00:00
Benjamin Kramer
3db5296619 DAGCombiner: Deduplicate code.
llvm-svn: 148217
2012-01-15 11:50:43 +00:00
Stepan Dyatkovskiy
2e727a1727 Cosmetic patch for r148215.
llvm-svn: 148216
2012-01-15 09:45:11 +00:00
Stepan Dyatkovskiy
d7b16b0e44 Fixup for r148132. Type replacement for LoopsProperties: from DenseMap to std::map, since we need to keep a valid pointer to properties of current loop.
Message for r148132:
LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache).

llvm-svn: 148215
2012-01-15 09:44:07 +00:00
Chandler Carruth
d328cc2c87 Remove SetWorkingDirectory from the Process interface. Nothing in LLVM
or Clang is using this, and it would be hard to use it correctly given
the thread hostility of the function. Also, it never checked the return
which is rather dangerous with chdir. If someone was in fact using this,
please let me know, as well as what the usecase actually is so that
I can add it back and make it more correct and secure to use. (That
said, it's never going to be "safe" per-se, but we could at least
document the risks...)

llvm-svn: 148211
2012-01-15 08:41:35 +00:00
David Blaikie
e3b1a7c2d7 Remove dead code.
llvm-svn: 148206
2012-01-15 01:09:13 +00:00
Craig Topper
7380799e4a Truncate of undef is just undef of smaller size.
llvm-svn: 148205
2012-01-15 01:05:11 +00:00
Craig Topper
0c4ab86d2c Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem.
llvm-svn: 148196
2012-01-14 18:29:57 +00:00
Craig Topper
ddc2e1091e Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.
llvm-svn: 148194
2012-01-14 18:14:53 +00:00
Duncan Sands
96dee83647 Speculatively revert commit 148175 (rafael), to see if this fixes
non-determinism in the 32 bit dragonegg buildbot.  Original commit
message:
Only emit the Leh_func_endN symbol when needed.

llvm-svn: 148191
2012-01-14 17:16:48 +00:00
Andrew Trick
071cb0a076 Fix a corner case hit by redundant phi elimination running after LSR.
Fixes PR11761: bad IR w/ redundant Phi elim

llvm-svn: 148177
2012-01-14 03:17:23 +00:00
Rafael Espindola
a4e515db51 Only emit the Leh_func_endN symbol when needed.
llvm-svn: 148175
2012-01-14 02:36:51 +00:00
Andrew Trick
4bf8728f07 misched: Initial code for building an MI level scheduling DAG
llvm-svn: 148174
2012-01-14 02:17:18 +00:00
Andrew Trick
dcb9435036 Move physreg dependency generation into aptly named addPhysRegDeps.
llvm-svn: 148173
2012-01-14 02:17:15 +00:00
Andrew Trick
1fd0adb573 misched: Added ScheduleDAGInstrs::IsPostRA
llvm-svn: 148172
2012-01-14 02:17:12 +00:00
Andrew Trick
6b08526310 misched: Invoke the DAG builder on each sequence of schedulable instructions.
llvm-svn: 148171
2012-01-14 02:17:09 +00:00
Andrew Trick
ce507adb56 Move things around to make the file navigable, even though it will probably be split up later.
llvm-svn: 148170
2012-01-14 02:17:06 +00:00
Evan Cheng
c0e7b19ff0 After r147827 and r147902, it's now possible for unallocatable registers to be
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
        cbnz    r6, LBB89_12
...
LBB89_12:
        ble     LBB89_1

The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.

rdar://10676853

llvm-svn: 148168
2012-01-14 01:53:46 +00:00
Chad Rosier
4a705ae81a Fix pasto from r146196.
llvm-svn: 148167
2012-01-14 01:50:21 +00:00
Dan Gohman
4539e2a975 Fix an unused variable warning that Chad noticed.
llvm-svn: 148164
2012-01-14 00:47:44 +00:00
Rafael Espindola
2b55c13cf1 Remove previous commit while I debug the bot failures.
llvm-svn: 148156
2012-01-13 23:28:50 +00:00
Jakob Stoklund Olesen
b1f7df8d8b Use RegisterTuples to generate pseudo-registers.
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.

This makes the call clobber lists longer, but I intend to get rid of
those soon.

llvm-svn: 148151
2012-01-13 22:55:42 +00:00
Rafael Espindola
3a35eeb0aa Remove label that is not used anymore.
llvm-svn: 148150
2012-01-13 22:41:58 +00:00
Eli Friedman
a70048903b Speculatively revert r148132+r148133 to try and fix a buildbot failure.
llvm-svn: 148149
2012-01-13 22:34:39 +00:00
Andrew Trick
796cca6eff Remove pointless mode line in .cpp file.
llvm-svn: 148143
2012-01-13 22:04:16 +00:00
Devang Patel
410d6214f9 Revert r148131, it was committed before it was ready.
llvm-svn: 148134
2012-01-13 19:28:58 +00:00
Stepan Dyatkovskiy
81514d2471 Cosmetic patch for r148132.
llvm-svn: 148133
2012-01-13 19:27:22 +00:00
Stepan Dyatkovskiy
94682abb75 LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache).
llvm-svn: 148132
2012-01-13 19:13:54 +00:00
Devang Patel
194ad5ead8 Refactor.
llvm-svn: 148131
2012-01-13 19:12:18 +00:00
Craig Topper
c1e3d46e07 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.
llvm-svn: 148112
2012-01-13 09:21:41 +00:00
Craig Topper
e75115a861 use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
llvm-svn: 148109
2012-01-13 08:32:21 +00:00
Craig Topper
e52c0484de Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
llvm-svn: 148108
2012-01-13 08:12:35 +00:00
Craig Topper
71ea42cc29 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32.
llvm-svn: 148106
2012-01-13 06:59:47 +00:00
Andrew Trick
85c44d1485 Added the MachineSchedulerPass skeleton.
llvm-svn: 148105
2012-01-13 06:30:30 +00:00
Andrew Trick
97340838f5 wrong filename
llvm-svn: 148103
2012-01-13 06:30:22 +00:00
Andrew Trick
117f29f574 80-col violation
llvm-svn: 148102
2012-01-13 06:30:19 +00:00
Craig Topper
0e34a8e58c Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750.
llvm-svn: 148101
2012-01-13 06:12:41 +00:00
Craig Topper
32812741b7 Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
llvm-svn: 148096
2012-01-13 05:04:25 +00:00
Jakob Stoklund Olesen
9ba097a208 Delete CodeInit and CodeRecTy from TableGen.
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

llvm-svn: 148092
2012-01-13 03:38:34 +00:00