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2758 Commits

Author SHA1 Message Date
Evan Cheng
90aa032f98 Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move. 
llvm-svn: 42774
 2007-10-08 22:16:29 +00:00
Dan Gohman
6df332f0cb Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
 2007-10-08 18:33:35 +00:00
Evan Cheng
090bfbebd1 Allow x86 compare to be commutable by default. 
llvm-svn: 42761
 2007-10-08 18:27:46 +00:00
Chris Lattner
fcccf4b6c4 disable this entirely: it is causing use of invalidated iterators and infinite looping. 
llvm-svn: 42739
 2007-10-07 22:00:31 +00:00
Chris Lattner
39dbb82db2 Fix many regressions on x86 by avoiding dereferencing the end iterator. 
llvm-svn: 42738
 2007-10-07 21:53:12 +00:00
Anton Korobeynikov
54ecd77023 Oops, I really wanted to commit this part also :) 
llvm-svn: 42700
 2007-10-06 16:39:43 +00:00
Anton Korobeynikov
34fefcf678 Move merge code into new helper function. 
llvm-svn: 42699
 2007-10-06 16:17:49 +00:00
Evan Cheng
dc95020e30 Added DAG xforms. e.g. 
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677
 2007-10-06 02:46:29 +00:00
Evan Cheng
9af50ee6ef Commute x86 cmove instructions by swapping the operands and change the condition 
to its inverse.
Testing this as llcbeta

llvm-svn: 42661
 2007-10-05 23:13:21 +00:00
Evan Cheng
e0e36e4a0e This is done. 
llvm-svn: 42656
 2007-10-05 22:34:59 +00:00
Evan Cheng
dc467c6323 Enable convertToThreeAddress for X86 by default. 
llvm-svn: 42655
 2007-10-05 22:31:10 +00:00
Evan Cheng
2b3122e56e INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can 
cause performance degradation.

llvm-svn: 42653
 2007-10-05 21:55:32 +00:00
Evan Cheng
688f34a273 In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. 
leal 1(%ecx), %edi, which requires 67H prefix.

llvm-svn: 42647
 2007-10-05 20:34:26 +00:00
Evan Cheng
b069dd6a25 Add support to convert more 64-bit instructions to 3-address instructions. 
llvm-svn: 42642
 2007-10-05 18:20:36 +00:00
Evan Cheng
f658191412 ADC and SBB uses EFLAGS. 
llvm-svn: 42640
 2007-10-05 17:59:57 +00:00
Dan Gohman
821635b63f Change a few more spaces to tabs in assembly output. 
llvm-svn: 42638
 2007-10-05 15:58:41 +00:00
Dan Gohman
950f96e456 Change a space to a tab in the assembly output of a .globl directive 
for consistency.

llvm-svn: 42637
 2007-10-05 15:54:58 +00:00
Evan Cheng
4e46ad06fe Testing convertToThreeeAddress as X86 llcbeta. 
llvm-svn: 42630
 2007-10-05 08:04:01 +00:00
Evan Cheng
6e5205d379 Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's. 
llvm-svn: 42624
 2007-10-05 01:34:55 +00:00
Evan Cheng
32766d3518 Not needed any more. 
llvm-svn: 42623
 2007-10-05 01:34:14 +00:00
Chris Lattner
4224151a44 add a note. 
llvm-svn: 42607
 2007-10-04 15:47:27 +00:00
Dan Gohman
30ba45b569 Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().

llvm-svn: 42585
 2007-10-03 19:26:29 +00:00
Chris Lattner
a31fa80185 add a note 
llvm-svn: 42579
 2007-10-03 17:10:03 +00:00
Chris Lattner
dfcb750656 Bill's example is still not enough to repro this, but it has other issues that 
seem significant as well.

llvm-svn: 42564
 2007-10-03 03:40:24 +00:00
Bill Wendling
c5fbf331ff Another micro-opt. 
llvm-svn: 42554
 2007-10-02 21:49:31 +00:00
Bill Wendling
c4a53b617f Another missed optimization with LICM. 
llvm-svn: 42552
 2007-10-02 21:43:06 +00:00
Bill Wendling
36f033e53e Small label changes. 
llvm-svn: 42549
 2007-10-02 21:02:53 +00:00
Bill Wendling
a7d5c36215 Now with source code. 
llvm-svn: 42548
 2007-10-02 21:01:16 +00:00
Bill Wendling
0159f0c5ba Now with LL code! 
llvm-svn: 42547
 2007-10-02 20:54:32 +00:00
Bill Wendling
48c27bf598 Another missed optimization. 
llvm-svn: 42546
 2007-10-02 20:42:59 +00:00
Bill Wendling
5e50716a6b Micro-optimization -- missed LICM opportunity. 
llvm-svn: 42542
 2007-10-02 19:55:05 +00:00
Evan Cheng
3537dbbd1e Refactor code to add load / store folded instructions -> register only 
instructions reverse map.

llvm-svn: 42509
 2007-10-01 23:44:33 +00:00
Evan Cheng
c863779cd4 Typo. X86comi doesn't read / write chain's. 
llvm-svn: 42492
 2007-10-01 18:12:48 +00:00
Gordon Henriksen
9b5a117d01 AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

llvm-svn: 42482
 2007-09-30 13:39:29 +00:00
Evan Cheng
f3c130a8b6 Enabling new condition code modeling scheme. 
llvm-svn: 42459
 2007-09-29 00:00:36 +00:00
Rafael Espindola
01b306e575 Refactor the memcpy lowering for the x86 target. 
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.

llvm-svn: 42433
 2007-09-28 12:53:01 +00:00
Evan Cheng
c2acb6f2e5 Stop inventing new words. :-) 
llvm-svn: 42429
 2007-09-28 01:35:02 +00:00
Evan Cheng
d3ff9d3ff7 Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS. 
llvm-svn: 42426
 2007-09-28 01:19:48 +00:00
Dan Gohman
50747737a5 TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets 
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.

llvm-svn: 42419
 2007-09-27 23:12:31 +00:00
Evan Cheng
d8ab90ae1f Use GR64 in 64-bit mode. 
llvm-svn: 42417
 2007-09-27 21:50:05 +00:00
Evan Cheng
826f0f94df Doh. Calls clobber EFLAGS. 
llvm-svn: 42413
 2007-09-27 19:01:55 +00:00
Evan Cheng
0f9e307353 - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). 
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372
 2007-09-26 21:31:07 +00:00
Evan Cheng
66eeb8440c Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf. 
llvm-svn: 42371
 2007-09-26 21:28:00 +00:00
Dale Johannesen
69595b587f Enable codegen for long double abs, sin, cos 
llvm-svn: 42368
 2007-09-26 21:10:55 +00:00
Evan Cheng
37ee6eba29 Typos: POPQ -> POPFQ, POPD -> POPFD. 
llvm-svn: 42348
 2007-09-26 06:38:29 +00:00
Chris Lattner
86e73ac224 move PR1160 here. 
llvm-svn: 42347
 2007-09-26 06:29:31 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Chris Lattner
2efd3899f2 move PR1264 here. 
llvm-svn: 42345
 2007-09-26 06:15:48 +00:00
Evan Cheng
5cb9dbaaa1 Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. 
llvm-svn: 42335
 2007-09-26 01:29:06 +00:00
Evan Cheng
38c7d5082a translateX86CC updates the last two operands. 
llvm-svn: 42333
 2007-09-26 00:45:55 +00:00