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3 Commits

Author SHA1 Message Date
Daniel Sanders
d13fea547a [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders
d201758a30 [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) 
This covers the case where fmax_a can be used to implement ISD::FABS.

llvm-svn: 191296
 2013-09-24 13:02:08 +00:00
Daniel Sanders
16a6e0ac3d [mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518. 
llvm-svn: 190522
 2013-09-11 12:39:25 +00:00