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14891 Commits

Author SHA1 Message Date
Nadav Rotem
f9d8f801d9 Add additional element-promotion tests. 
llvm-svn: 142442
 2011-10-18 23:05:33 +00:00
Nadav Rotem
e435b9e2fd Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Index starts with zero. 
llvm-svn: 142434
 2011-10-18 22:32:43 +00:00
Jim Grosbach
6110df7008 Tidy up formatting. 
llvm-svn: 142422
 2011-10-18 21:09:01 +00:00
Jim Grosbach
de82cec744 Tidy up formatting. 
llvm-svn: 142421
 2011-10-18 21:08:16 +00:00
Jim Grosbach
f0d2d6bfc1 Enable more encoded immediate tests. 
llvm-svn: 142415
 2011-10-18 20:20:51 +00:00
Jim Grosbach
8c1298946c More vmov lane testcases. 
llvm-svn: 142414
 2011-10-18 20:19:48 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Michael J. Spencer
f21a701890 llvm-objdump: Add static symbol table dumping. 
llvm-svn: 142404
 2011-10-18 19:32:17 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Owen Anderson
39a3d3305a Another failing encoding. 
llvm-svn: 142388
 2011-10-18 18:23:03 +00:00
Jim Grosbach
de8f8bec78 Fix NEON mul encoding tests. Wrong file contents previously. 
llvm-svn: 142387
 2011-10-18 18:14:55 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach
d2162f8c95 Remove duplicate test. 
llvm-svn: 142383
 2011-10-18 18:05:50 +00:00
Jim Grosbach
86d53ed3d4 Tidy up formatting. 
llvm-svn: 142382
 2011-10-18 18:05:16 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Jim Grosbach
93213f0ca9 Tidy up. 
llvm-svn: 142380
 2011-10-18 18:01:09 +00:00
Owen Anderson
593bfe68d2 Add a few more testcases. 
llvm-svn: 142379
 2011-10-18 17:57:31 +00:00
Owen Anderson
77f405511d Add several FIXME cases for ARM encodings. 
llvm-svn: 142377
 2011-10-18 17:50:22 +00:00
Bob Wilson
f78f688c02 Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

llvm-svn: 142371
 2011-10-18 17:34:51 +00:00
Bob Wilson
0273c767c8 Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS. 
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization.  For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.

llvm-svn: 142370
 2011-10-18 17:34:47 +00:00
Jim Grosbach
8c454cac49 Tests for 142365. 
llvm-svn: 142368
 2011-10-18 17:23:34 +00:00
Jim Grosbach
df6fb84ea5 Tidy up formatting. 
llvm-svn: 142367
 2011-10-18 17:22:53 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Justin Holewinski
361b3c9ff2 PTX: Fix disabling of MAD instruction selection 
llvm-svn: 142352
 2011-10-18 13:39:20 +00:00
Chad Rosier
eb469f466b Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916

llvm-svn: 142337
 2011-10-18 05:28:00 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Michael J. Spencer
00c39291ef Revert "llvm-objdump: Add static symbol table dumping." 
This reverts commit 0c30d4e4f5f9110c5a67bd0ca84444dc58697596.

llvm-svn: 142320
 2011-10-18 00:17:04 +00:00
Michael J. Spencer
8c590fd08d llvm-objdump: Add static symbol table dumping. 
llvm-svn: 142319
 2011-10-17 23:55:22 +00:00
Jim Grosbach
9266437a1f Enable a few more NEON immediate tests. 
llvm-svn: 142313
 2011-10-17 23:50:19 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Nick Lewycky
c551c1c5f9 Add support for a new extension to the .file directive: 
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.

llvm-svn: 142300
 2011-10-17 23:05:28 +00:00
Dan Gohman
5e2d8538d7 Teach the ARC optimizer about the !clang.arc.copy_on_escape metadata 
tag on objc_retainBlock calls, which indicates that they may be
optimized away. rdar://10211286.

llvm-svn: 142298
 2011-10-17 22:53:25 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Lang Hames
5ef0a146b9 Fixed quoting on default data layout option. 
llvm-svn: 142286
 2011-10-17 21:54:43 +00:00
Bill Wendling
2c5486d770 Add support for the Objective-C personality function to the instruction 
combining of the landingpad instruction. The ObjC personality function acts
almost identically to the C++ personality function. In particular, it uses
"null" as a "catch-all" value.

llvm-svn: 142256
 2011-10-17 21:20:24 +00:00
Nadav Rotem
b03ef2cd0b Add CHECKs and document PR11158. 
llvm-svn: 142240
 2011-10-17 20:23:23 +00:00
Nadav Rotem
2d3d696b51 stabalize tests by specifying the exact sse level 
llvm-svn: 142229
 2011-10-17 19:45:38 +00:00
Dan Gohman
13624a6c83 Suppress partial retain+release elimination when there's a 
possibility that it will span multiple CFG diamonds/triangles which
could have different controlling predicates.  rdar://10282956

llvm-svn: 142222
 2011-10-17 18:48:25 +00:00
Bill Wendling
584c5f9c62 Correct over-zealous removal of hack. 
Some code want to check that *any* call within a function has the 'returns
twice' attribute, not just that the current function has one.

llvm-svn: 142221
 2011-10-17 18:43:40 +00:00
Bill Wendling
c5372de48f Temporarily XFAIL waiting for a fix. 
llvm-svn: 142215
 2011-10-17 18:25:32 +00:00
Michael J. Spencer
277eaf9f19 llvm-objdump: Add -s, which prints the contents of each section. 
llvm-svn: 142199
 2011-10-17 17:13:22 +00:00
Michael J. Spencer
689903addb llvm-objdump: Add tests. 
llvm-svn: 142198
 2011-10-17 17:13:05 +00:00
Hal Finkel
d65adcde2d use FileCheck and not grep in new tests 
llvm-svn: 142189
 2011-10-17 16:01:41 +00:00
Nadav Rotem
b2979db708 Clean the triple, add check lines. 
llvm-svn: 142183
 2011-10-17 07:07:51 +00:00
Nadav Rotem
77004e845a Previously v2i32 vectors were legalized to v4i32. Now, they are legalized to 
v2i64. These tests do not check MMX nor zmoving into them.

llvm-svn: 142182
 2011-10-17 06:59:01 +00:00
Hal Finkel
8be5b30fa8 Test case for CanLowerReturn fix (r141981) 
llvm-svn: 142172
 2011-10-17 04:03:59 +00:00
Hal Finkel
b128cda81b Add PPC 440 scheduler and some associated tests (new files) 
llvm-svn: 142171
 2011-10-17 04:03:55 +00:00
Chandler Carruth
9c33ff8a8b Add a routine to swap branch instruction operands, and update any 
profile metadata at the same time. Use it to preserve metadata attached
to a branch when re-writing it in InstCombine.

Add metadata to the canonicalize_branch InstCombine test, and check that
it is tranformed correctly.

Reviewed by Nick Lewycky!

llvm-svn: 142168
 2011-10-17 01:11:57 +00:00
Nadav Rotem
eeb400322e Add tripple and stabalize a few more tests. 
llvm-svn: 142158
 2011-10-16 21:20:54 +00:00
Nadav Rotem
d3f24f0fe5 Add triple to tests. 
llvm-svn: 142154
 2011-10-16 20:53:20 +00:00
Nadav Rotem
60c9b81158 fix a typo in the test 
llvm-svn: 142153
 2011-10-16 20:43:41 +00:00
Nadav Rotem
8ed6f090ef Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00
Nick Lewycky
f590cdf15e Oops! Fix testcase. 
llvm-svn: 142151
 2011-10-16 20:20:15 +00:00
Nick Lewycky
c8b7f776e6 When looking for dependencies on the src pointer, scan the src pointer. Scanning 
on the memcpy call will pull up other unrelated stuff. Fixes PR11142.

llvm-svn: 142150
 2011-10-16 20:13:32 +00:00
Nadav Rotem
22398874f8 Remove the the test which checks the saving of a vector of booleans into memory. 
The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.

llvm-svn: 142149
 2011-10-16 19:06:06 +00:00
Craig Topper
6c900d9810 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Nadav Rotem
a733f43137 Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was 
no pattern.

llvm-svn: 142130
 2011-10-16 10:02:06 +00:00
Craig Topper
2cd868184c Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper
91b4292682 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00
Chris Lattner
321335142c Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
 2011-10-16 04:47:35 +00:00
Craig Topper
4c6357d4af Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
NAKAMURA Takumi
6226fbe339 test/Makefile: Inspect $(PROJ_OBJ_ROOT)/tools/clang/Makefile instead of $(PROJ_SRC_ROOT)/tools/clang for "check-all". 
llvm-svn: 142100
 2011-10-16 02:54:14 +00:00
Craig Topper
62e63d9bb9 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Nico Weber
bca9567da0 Let this test pass even if 'int' is somewhere in its directory path. 
On my machine, grep matched:

  ; ModuleID = '/Volumes/MacintoshHD2/src/chrome-git/src/third_party/llvm/test/Linker/2011-08-18-unique-debug-type.ll'
  !9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]

Explicitly filter out the ModuleID line.

llvm-svn: 142077
 2011-10-15 18:07:16 +00:00
Andrew Trick
0ef2965563 Fix SCEVExpander assert during LSR: "argument of incompatible type". 
Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.

llvm-svn: 142058
 2011-10-15 06:19:55 +00:00
Eli Friedman
c8d798d91e Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. 
llvm-svn: 142022
 2011-10-14 23:58:49 +00:00
Owen Anderson
96976108b1 Update test for disabling of code/data marker labels in ELF. 
llvm-svn: 142003
 2011-10-14 21:12:55 +00:00
Torok Edwin
ab8624db55 OCaml bindings: add some missing functions and testcases. 
The C bindings exposed some APIs that weren't covered by the OCaml bindings

llvm-svn: 141997
 2011-10-14 20:38:33 +00:00
Torok Edwin
39d89ea3b3 OCaml bindings: fix infinite recursion on string_of_lltype 
llvm-svn: 141994
 2011-10-14 20:38:14 +00:00
Jakob Stoklund Olesen
6f0c76740b Update live-in lists when splitting critical edges. 
Fixes PR10814. Patch by Jan Sjödin!

llvm-svn: 141960
 2011-10-14 17:25:46 +00:00
Craig Topper
0a11eb1b21 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Craig Topper
6b2120a8e1 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141939
 2011-10-14 03:21:46 +00:00
Jakob Stoklund Olesen
98e48aef6f Add value numbers when spilling dead defs. 
When spilling around an instruction with a dead def, remember to add a
value number for the def.

The missing value number wouldn't normally create problems since there
would be an incoming live range as well.  However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.

The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.

This fixes part of PR11125.

llvm-svn: 141923
 2011-10-14 00:34:31 +00:00
Michael J. Spencer
10caa055b0 ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev! 
llvm-svn: 141901
 2011-10-13 22:30:10 +00:00
Michael J. Spencer
4ee36e15ad llvm-object: Add inline relocation information to disassembly. 
llvm-svn: 141897
 2011-10-13 22:17:18 +00:00
Andrew Trick
923129b028 Reapply r141870, SCEV expansion of post-inc. 
Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.

llvm-svn: 141895
 2011-10-13 21:55:29 +00:00
Andrew Trick
109f7dbd1e Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed. 
llvm-svn: 141873
 2011-10-13 17:58:24 +00:00
Andrew Trick
05d7cb17d5 LSR: Reuse the post-inc expansion of expressions. 
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.

llvm-svn: 141870
 2011-10-13 17:31:47 +00:00
Benjamin Kramer
a705595096 Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs. 
llvm-svn: 141863
 2011-10-13 14:27:54 +00:00
Kalle Raiskila
15993a5d28 Mark 'branch indirect' instruction as an indirect branch. 
Not having it confused assembly printing of jumptables.

llvm-svn: 141862
 2011-10-13 11:40:03 +00:00
Bill Wendling
dcd9c25744 More closely follow libgcc, which has code after the `ret' instruction to 
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859
 2011-10-13 08:24:19 +00:00
Bill Wendling
2a571af745 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
 2011-10-13 07:48:07 +00:00
Bill Wendling
a6bf25f30a Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I. 
llvm-svn: 141856
 2011-10-13 07:42:32 +00:00
Craig Topper
eb29e18c9b Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141854
 2011-10-13 07:09:14 +00:00
Jakob Stoklund Olesen
f38db50fed Also inflate register classes around inline asm. 
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

llvm-svn: 141836
 2011-10-12 23:37:40 +00:00
Bill Wendling
60bfb5d707 We need to verify that the machine instruction we're using as a replacement for 
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>

llvm-svn: 141830
 2011-10-12 23:03:40 +00:00
Lang Hames
069669eb13 Removed colons from some target datalayout strings in test, since they don't match the required format. 
llvm-svn: 141825
 2011-10-12 22:24:17 +00:00
Kevin Enderby
974c799a5a Finish supporting cpp #file/line comments in assembler for error messages. So 
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895

llvm-svn: 141814
 2011-10-12 21:38:39 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach
2a501996ab ARM encoding tests for STC. 
llvm-svn: 141787
 2011-10-12 17:36:13 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions. 
llvm-svn: 141786
 2011-10-12 17:34:41 +00:00
Jakob Stoklund Olesen
2611cc2520 Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746
 2011-10-12 00:06:23 +00:00
Bob Wilson
20cc1d9f51 Make this test more specific. There are 3 stats that matched "machine-licm". 
llvm-svn: 141741
 2011-10-11 23:34:31 +00:00
Eric Christopher
57c57a3260 Add a new wrapper node for a DILexicalBlock that encapsulates it and a 
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.

This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.

Part of rdar://10246360

llvm-svn: 141729
 2011-10-11 22:59:11 +00:00
Jim Grosbach
d2cfc2b31f ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
 2011-10-11 21:55:36 +00:00
Bill Wendling
a1c238d8bf Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
llvm-svn: 141716
 2011-10-11 21:40:47 +00:00
Cameron Zwarich
fac176ac51 Fix PR11106 by correcting a typo that has been in the code for over a year. This 
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.

llvm-svn: 141713
 2011-10-11 21:26:40 +00:00
Jim Grosbach
313a74d565 Update test for r141704. 
llvm-svn: 141705
 2011-10-11 20:18:50 +00:00
Devang Patel
3811b42be0 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689
 2011-10-11 18:09:58 +00:00
Nadav Rotem
6ddbd1308b Add support for legalization of vector SHL/SRA/SRL instructions 
llvm-svn: 141667
 2011-10-11 14:36:35 +00:00
Nick Lewycky
6bd023fab9 Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.

llvm-svn: 141653
 2011-10-11 06:58:11 +00:00
Craig Topper
f95d9bd513 Test case for X86 LZCNT instruction selection. 
llvm-svn: 141652
 2011-10-11 06:47:01 +00:00
Craig Topper
c498c5c0e6 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Cameron Zwarich
211901eb9f Add a test for PR10565. 
llvm-svn: 141647
 2011-10-11 06:10:37 +00:00
Cameron Zwarich
a34d748f83 Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's 
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

llvm-svn: 141646
 2011-10-11 06:10:30 +00:00
Bill Wendling
2606813218 Test simplification that Ana Pazos noticed. 
llvm-svn: 141644
 2011-10-11 04:43:15 +00:00
Craig Topper
7ae42fbd7e Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Nick Lewycky
509687695f Also create a shndx even if there are no symbols. This lets us test 
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.

llvm-svn: 141641
 2011-10-11 03:54:50 +00:00
NAKAMURA Takumi
00636555f2 test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts. 
llvm-svn: 141640
 2011-10-11 03:41:03 +00:00
Andrew Trick
d36852e6b1 Move replaceCongruentIVs into SCEVExapander and bias toward "expanded" 
IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.

llvm-svn: 141633
 2011-10-11 02:28:51 +00:00
Akira Hatanaka
2da85501f4 Test cases for 64-bit load and store instructions. 
llvm-svn: 141631
 2011-10-11 01:52:31 +00:00
Lang Hames
386b01379a Added a testcase for r141599, rdar://problem/10063881. 
llvm-svn: 141628
 2011-10-11 01:32:10 +00:00
Bill Wendling
cb617ae8e0 Add testcase for PR11107. 
llvm-svn: 141607
 2011-10-11 00:26:57 +00:00
Devang Patel
e6091c61c7 Revert r141569 and r141576. 
llvm-svn: 141594
 2011-10-10 23:18:02 +00:00
Bill Wendling
7121342ad5 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Eli Friedman
7188ba35cb Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00
Nick Lewycky
73e4d372d0 Add support for dumping section headers to llvm-objdump. This uses the same 
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.

llvm-svn: 141579
 2011-10-10 21:21:34 +00:00
Devang Patel
d6f05a47c1 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
llvm-svn: 141576
 2011-10-10 20:32:03 +00:00
Nadav Rotem
38187aec17 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.

llvm-svn: 141570
 2011-10-10 19:31:45 +00:00
Devang Patel
c149f390c6 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
 2011-10-10 19:09:20 +00:00
Benjamin Kramer
c498279bec X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
llvm-svn: 141563
 2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen
f46c756068 Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562
 2011-10-10 18:30:16 +00:00
Bill Wendling
7cba44defc Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
 2011-10-10 18:27:30 +00:00
Benjamin Kramer
abcce0b8be XFAIL tblgen tests on leak checkers. 
llvm-svn: 141533
 2011-10-10 13:09:59 +00:00
Bill Wendling
94258753c7 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
 2011-10-10 07:24:23 +00:00
Craig Topper
9b7ab95570 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
b49557d06d Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
2817bbdeaf Add missing test case for r141410. 
llvm-svn: 141498
 2011-10-08 18:06:54 +00:00
Andrew Trick
9d4d1281ad Unit test for LSR phi reuse in r141442. 
llvm-svn: 141472
 2011-10-08 02:34:51 +00:00
Michael J. Spencer
e497728e76 llvm-objdump: Add relocation and archive support. 
llvm-svn: 141451
 2011-10-08 00:18:30 +00:00
Jim Grosbach
6322a90e2d Enable ARM mode VDUP(scalar) tests. 
llvm-svn: 141447
 2011-10-07 23:57:03 +00:00
Jim Grosbach
94980a23e6 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
David Greene
ae3329d597 Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

llvm-svn: 141378
 2011-10-07 18:25:05 +00:00
Evan Cheng
99b25c827c High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
llvm-svn: 141371
 2011-10-07 17:21:44 +00:00
Bob Wilson
b55a64ae72 Reenable tail calls for iOS 5.0 and later. 
llvm-svn: 141370
 2011-10-07 17:17:49 +00:00
Bob Wilson
d8856e17fe Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
llvm-svn: 141368
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov
0944a4c5cc Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!

llvm-svn: 141365
 2011-10-07 16:15:08 +00:00
Duncan Sands
559ef2f491 Teach GVN to also propagate switch cases. For example, in this code 
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.

llvm-svn: 141360
 2011-10-07 08:29:06 +00:00
Craig Topper
761bf0e7d3 Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
llvm-svn: 141358
 2011-10-07 07:02:24 +00:00
Craig Topper
71e09ffe7b Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
llvm-svn: 141354
 2011-10-07 05:53:50 +00:00
Craig Topper
f083691b6d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Jim Grosbach
53b2b56db8 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead. 
llvm-svn: 141321
 2011-10-06 22:04:05 +00:00
Jim Grosbach
ec12700fe4 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141318
 2011-10-06 21:32:50 +00:00
Jim Grosbach
17ae6aae38 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141316
 2011-10-06 21:28:30 +00:00
David Greene
0ed16506bf Make Test More Thorough 
Check that all ADD patters are processed.

Add a SUB test.

llvm-svn: 141314
 2011-10-06 21:20:44 +00:00
Peter Collingbourne
78a1609fa2 s/tblgen/llvm-tblgen/g in a few missed places, including the tests 
llvm-svn: 141294
 2011-10-06 13:39:59 +00:00
Torok Edwin
be951e90d4 ocaml bindings: add llvm_ipo based on IPO.h 
llvm-svn: 141284
 2011-10-06 12:12:27 +00:00
Torok Edwin
1c3d252cfd add more tests for the OCaml bindings 
llvm-svn: 141283
 2011-10-06 12:12:12 +00:00
Craig Topper
2614f6f120 Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
llvm-svn: 141274
 2011-10-06 06:44:41 +00:00
Cameron Zwarich
cc5f846d58 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

llvm-svn: 141247
 2011-10-05 23:38:50 +00:00
David Greene
882705e63e Update Test for Multidefs 
Update the MultiPat.td test to create some defs via multidefs.

llvm-svn: 141235
 2011-10-05 22:42:48 +00:00
David Greene
4a605dc02c Add a Multidef Test 
Add a simple test for multidefs.

llvm-svn: 141234
 2011-10-05 22:42:47 +00:00
Eli Friedman
dd48bb30de PR11061: Make simplifylibcalls fold strcmp("", x) correctly. 
While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp.

llvm-svn: 141227
 2011-10-05 22:27:16 +00:00
Jim Grosbach
254b9ed208 Revert 141203. InstCombine is looping on unit tests. 
llvm-svn: 141209
 2011-10-05 20:44:29 +00:00
Rafael Espindola
8247f7a5dd Check for the returns_twice attribute in callsFunctionThatReturnsTwice. This 
fixes PR11038, but there are still some cleanups to be done.

llvm-svn: 141204
 2011-10-05 20:05:13 +00:00
Jim Grosbach
a03dd9189f Update InstCombine worklist after instruction transform is complete. 
When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.

rdar://10238555

llvm-svn: 141203
 2011-10-05 20:05:00 +00:00
Dan Gohman
779ae47721 Make this test less sensitive to codegen optimizations. 
llvm-svn: 141195
 2011-10-05 18:13:08 +00:00
Owen Anderson
2d1e930b65 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
llvm-svn: 141190
 2011-10-05 17:16:40 +00:00
Duncan Sands
f7df28c1f5 GVN does simple propagation of conditions: when it sees a conditional 
branch "br i1 %x, label %if_true, label %if_false" then it replaces
"%x" with "true" in places only reachable via the %if_true arm, and
with "false" in places only reachable via the %if_false arm.  Except
that actually it doesn't: if value numbering shows that %y is equal
to %x then, yes, %y will be turned into true/false in this way, but
any occurrences of %x itself are not transformed.  Fix this.  What's
more, it's often the case that %x is an equality comparison such as
"%x = icmp eq %A, 0", in which case every occurrence of %A that is
only reachable via the %if_true arm can be replaced with 0.  Implement
this and a few other variations on this theme.  This reduces the number
of lines of LLVM IR in "GCC as one big file" by 0.2%.  It has a bigger
impact on Ada code, typically reducing the number of lines of bitcode
by around 0.4% by removing repeated compiler generated checks.  Passes
the LLVM nightly testsuite and the Ada ACATS testsuite.

llvm-svn: 141177
 2011-10-05 14:28:49 +00:00
Duncan Sands
348e8c285a Generalize GVN's conditional propagation logic slightly: 
it's OK for the false/true destination to have multiple
predecessors as long as the extra ones are dominated by
the branch destination.

llvm-svn: 141176
 2011-10-05 14:17:01 +00:00
Andrew Trick
b4cabec37a Missing test case for r141164. 
llvm-svn: 141166
 2011-10-05 06:23:32 +00:00
Owen Anderson
e255773f3d Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
llvm-svn: 141135
 2011-10-04 23:26:17 +00:00
Jim Grosbach
386f7cb041 Tidy up formatting. 
llvm-svn: 141123
 2011-10-04 21:43:51 +00:00
Jim Grosbach
f3373734b4 Un-XFAIL file. Comment out individual failing instructions. 
llvm-svn: 141117
 2011-10-04 21:16:42 +00:00
Jim Grosbach
6f00406f92 Tidy up formatting. 
llvm-svn: 141115
 2011-10-04 20:52:57 +00:00
Jim Grosbach
0db58d15e6 Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup. 
llvm-svn: 141114
 2011-10-04 20:50:05 +00:00
Jim Grosbach
3df5c47ec8 Un-XFAIL file. Fix incorrect CHECK line. General format cleanup. 
llvm-svn: 141113
 2011-10-04 20:46:49 +00:00
Jim Grosbach
4770714494 Tidy up formatting. 
llvm-svn: 141111
 2011-10-04 20:42:35 +00:00
Jim Grosbach
dee6bd4517 Un-XFAIL file. Fix incorrect CHECK line. 
llvm-svn: 141110
 2011-10-04 20:42:09 +00:00
Jim Grosbach
d7449dd23f Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
llvm-svn: 141108
 2011-10-04 20:34:11 +00:00
David Greene
10cf9ec1db Test Operand Arguments 
Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.

llvm-svn: 141102
 2011-10-04 18:55:40 +00:00
Jim Grosbach
58f067b61b Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
llvm-svn: 141099
 2011-10-04 18:43:15 +00:00
Jim Grosbach
93ad98accb Tidy up. Formatting. 
llvm-svn: 141096
 2011-10-04 17:49:45 +00:00
David Dean
b0f6751041 Fix PR9833/PR11054 (patch provided by Patrik Hägglund) 
llvm-svn: 141092
 2011-10-04 16:26:41 +00:00
Craig Topper
9d32602cfd Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Andrew Trick
c60e2addd9 LSR should avoid redundant edge splitting. 
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"

llvm-svn: 141059
 2011-10-04 03:50:44 +00:00
Andrew Trick
f9b98a3c3e Unit test for r140919, loop unroll heuristics. 
llvm-svn: 141049
 2011-10-04 00:07:02 +00:00
Jim Grosbach
8170db143e Tidy up. These tests are covered in the .s file tests now. 
llvm-svn: 141047
 2011-10-03 23:40:13 +00:00
Jim Grosbach
f38874e79e ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach
c69258c747 ARM parsing/encoding for VCMP/VCMPE. 
llvm-svn: 141038
 2011-10-03 22:30:24 +00:00
Akira Hatanaka
0a697c10ae Move CHECK after entry label. 
llvm-svn: 141030
 2011-10-03 21:24:30 +00:00
Akira Hatanaka
76c268271d Add support for 64-bit logical NOR. 
llvm-svn: 141029
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
ae50204423 Add support for 64-bit count leading ones and zeros instructions. 
llvm-svn: 141028
 2011-10-03 21:16:50 +00:00
Jim Grosbach
21a9f8f50f ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Akira Hatanaka
6c6ff6fde7 Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Jim Grosbach
0e385170ee Update test for 141010. 
llvm-svn: 141022
 2011-10-03 20:58:08 +00:00
Akira Hatanaka
e3c1d7eac0 Add support for 64-bit integer multiply instructions. 
llvm-svn: 141017
 2011-10-03 20:01:11 +00:00
Jim Grosbach
1651804363 Tidy up a bit. Formatting. 
llvm-svn: 141010
 2011-10-03 17:59:31 +00:00
Craig Topper
df04bee9b2 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
llvm-svn: 141007
 2011-10-03 17:28:23 +00:00
Rafael Espindola
4700f53cee Add the returns_twice attribute to LLVM. 
llvm-svn: 141001
 2011-10-03 14:45:37 +00:00
Craig Topper
4456c94f70 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
llvm-svn: 140997
 2011-10-03 08:14:29 +00:00
Craig Topper
a3372bd949 Test updates that were supposed to go with r140993. 
llvm-svn: 140994
 2011-10-03 07:53:59 +00:00
Nick Lewycky
4898eef762 Reapply r140979 with fix! We never did get a testcase, but careful review of the 
logic by David Meyer revealed this bug.

llvm-svn: 140992
 2011-10-03 07:10:45 +00:00
Torok Edwin
b7495041db attempt to fix ocaml bindings: landing pads 
llvm-svn: 140991
 2011-10-03 06:41:46 +00:00
Nick Lewycky
79fec8116f Revert r140979 due to reports of bootstrap failure. 
llvm-svn: 140980
 2011-10-03 05:14:59 +00:00
Nick Lewycky
a760a29395 Add one more case we compute a max trip count. 
llvm-svn: 140979
 2011-10-03 01:03:57 +00:00
Craig Topper
f776e3b410 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
llvm-svn: 140974
 2011-10-02 21:08:12 +00:00
Craig Topper
5c8feca34f Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
llvm-svn: 140971
 2011-10-02 16:56:09 +00:00
Nick Lewycky
7cd1bfb89d Add a new icmp+select optz'n. Also shows off the load(cst) folding added in 
r140966.

llvm-svn: 140969
 2011-10-02 10:37:37 +00:00
Craig Topper
43fd621df8 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
Bill Wendling
98db234c02 Filecheck-ize. 
llvm-svn: 140904
 2011-09-30 23:40:29 +00:00
Bill Wendling
252b649025 Add new line at end of file. 
llvm-svn: 140903
 2011-09-30 23:21:11 +00:00
Bill Wendling
fcf3096d9b When inferring the pointer alignment, if the global doesn't have an initializer 
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.

For instance, in file A.c:

   struct S s;

In file B.c:
   struct {
     // something long
   };
   extern S s;

   void foo() {
     struct S p = s;
     // ...
   }

this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.

llvm-svn: 140902
 2011-09-30 23:19:55 +00:00
David Greene
7a9ac03042 Test More Complicated Lists 
Test of indexing lists of lists of lists works.  This also exercises
some operators.

llvm-svn: 140884
 2011-09-30 20:59:52 +00:00
David Greene
c5830e015f Test VarListElementInit:: resolveListElementReference 
Add a TableGen test to check if indexing lists of lists works.

llvm-svn: 140883
 2011-09-30 20:59:51 +00:00
Akira Hatanaka
5479850400 Remove unnecessary checking of register operands. 
llvm-svn: 140872
 2011-09-30 19:18:24 +00:00
Akira Hatanaka
c9268767d6 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Jim Grosbach
d35eaaeb6e float comparison to double 'zero' constant can just be a float 'zero.' 
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.

We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
  %conv = fpext float %x to double
  %cmp = fcmp olt double %conv, 0.000000e+00
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}

Into:
define float @bar(float %x) nounwind readnone optsize ssp {
  %cmp = fcmp olt float %x, 0.000000e+00   ; <---- This
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}


rdar://10215914

llvm-svn: 140869
 2011-09-30 18:45:50 +00:00
Jim Grosbach
44047da675 ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Akira Hatanaka
ffa28d49f1 Check values of immediate operands. 
llvm-svn: 140860
 2011-09-30 17:19:21 +00:00
Duncan Sands
14b9c222c6 Add forgotten tests that the cleanup flag is cleared if there 
is a catch-all landingpad clause.

llvm-svn: 140858
 2011-09-30 17:00:34 +00:00
Duncan Sands
b4c8b2d9fa Inlining often produces landingpad instructions with repeated 
catch or repeated filter clauses.  Teach instcombine a bunch
of tricks for simplifying landingpad clauses.  Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function.  Probably
someone should add the ObjC++ personality function.  I didn't as
I don't know anything about it.

llvm-svn: 140852
 2011-09-30 13:12:16 +00:00
Akira Hatanaka
dcd69c2e07 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
4bdb4b1958 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Akira Hatanaka
50a4f6d570 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825
 2011-09-29 23:52:13 +00:00
Dan Gohman
7dca165e93 When eliminating unnecessary retain+autorelease on return values, 
handle the case where the retain is in a different basic block.
rdar://10210274.

llvm-svn: 140815
 2011-09-29 22:27:34 +00:00
Dan Gohman
2df048a94b Don't eliminate objc_retainBlock calls on stack objects if the 
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.

llvm-svn: 140814
 2011-09-29 22:25:23 +00:00
Akira Hatanaka
70be05d5d0 Mips64 arithmetic and logical instructions with two source registers. 
llvm-svn: 140806
 2011-09-29 20:37:56 +00:00
Andrew Trick
e1d5ae73ac LSR: rewrite inner loops only. 
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.

llvm-svn: 140762
 2011-09-29 01:33:38 +00:00
Andrew Trick
75c6a45d08 whitespace 
llvm-svn: 140761
 2011-09-29 01:31:48 +00:00
Justin Holewinski
4966d44b44 PTX: Add new patterns for bitconvert and any_extend 
llvm-svn: 140753
 2011-09-29 01:13:12 +00:00
Evan Cheng
1e53900b70 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296

llvm-svn: 140733
 2011-09-28 23:16:31 +00:00
Eli Friedman
81fc13efd2 PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. 
llvm-svn: 140723
 2011-09-28 21:00:25 +00:00
Justin Holewinski
2f96de340f PTX: MC-ize the PTX back-end (patch 1 of N) 
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

llvm-svn: 140697
 2011-09-28 14:32:04 +00:00
James Molloy
c4fcff419c Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Andrew Trick
5167b59724 Test case for r140670: indvars should hoist sext. 
llvm-svn: 140671
 2011-09-28 02:13:32 +00:00
Eli Friedman
f4f4a75d2b PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls. 
llvm-svn: 140666
 2011-09-28 00:34:27 +00:00
Jakob Stoklund Olesen
2bf243f464 Remove X86-dependent stuff from SSEDomainFix. 
This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

llvm-svn: 140659
 2011-09-27 23:50:46 +00:00
Jim Grosbach
b503a2183e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647
 2011-09-27 22:18:54 +00:00
NAKAMURA Takumi
8095f04e96 test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build. 
llvm-svn: 140641
 2011-09-27 21:54:50 +00:00
Benjamin Kramer
355b353595 Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit. 
If someone prefers %tmp42 to %42, run instnamer.

llvm-svn: 140634
 2011-09-27 20:39:19 +00:00
Michael J. Spencer
89e83b38cd Add binary archive support to llvm-nm. 
llvm-svn: 140627
 2011-09-27 19:37:18 +00:00
Michael J. Spencer
6510b463d3 Unbreak tests. 
llvm-svn: 140622
 2011-09-27 19:06:37 +00:00
Justin Holewinski
a50e29abd6 PTX: Add support for sitofp in backend 
llvm-svn: 140593
 2011-09-27 01:04:47 +00:00
Bill Wendling
589336d854 Split the landing pad basic block with the correct function. Also merge the 
split landingpad instructions into a PHI node.
PR11016

llvm-svn: 140592
 2011-09-27 00:59:31 +00:00
Eli Friedman
db69f84663 Last batch of test conversions to new atomic instructions. 
llvm-svn: 140585
 2011-09-27 00:17:29 +00:00
Eli Friedman
3db429c878 Convert a bunch more tests over to the new atomic instructions. 
llvm-svn: 140582
 2011-09-26 23:15:09 +00:00
Owen Anderson
bfb83aae27 Fix an incorrect decoder test. 
llvm-svn: 140579
 2011-09-26 23:08:34 +00:00
Owen Anderson
c811b1bed2 Remove incorrect testcases. 
llvm-svn: 140572
 2011-09-26 22:13:55 +00:00
Eli Friedman
d01fc33809 Convert more tests to new atomic instructions. 
llvm-svn: 140567
 2011-09-26 21:36:10 +00:00
Eli Friedman
6aaaadc188 Convert more tests over to the new atomic instructions. 
I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.

The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.

llvm-svn: 140566
 2011-09-26 21:30:17 +00:00
Eli Friedman
56e68f7271 Convert more tests over to the new atomic instructions. 
llvm-svn: 140559
 2011-09-26 20:27:49 +00:00
Eli Friedman
ed450a3064 Upgrade a couple more tests to the new atomic instructions. 
llvm-svn: 140558
 2011-09-26 20:15:56 +00:00
Eli Friedman
9c1a430966 Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions. 
llvm-svn: 140557
 2011-09-26 20:15:28 +00:00
Eli Friedman
32d22b6d3f Fix this test so it doesn't fail on Mac. 
llvm-svn: 140553
 2011-09-26 19:13:47 +00:00
Justin Holewinski
52c50104d7 PTX: Fix detection of stack load/store vs. global load/store, as well as fix the 
printing of local offsets

llvm-svn: 140547
 2011-09-26 18:57:22 +00:00
James Molloy
d63e75cd59 Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. 
llvm-svn: 140539
 2011-09-26 17:40:42 +00:00
Justin Holewinski
443a122ac3 PTX: Add .align tests to stack object test file 
llvm-svn: 140537
 2011-09-26 16:20:38 +00:00