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Commit Graph

96629 Commits

Author SHA1 Message Date
Matthias Braun
cf84f537f1 Represent RegUnit liveness with LiveRange instance
Previously LiveInterval has been used, but having a spill weight and
register number is unnecessary for a register unit.

llvm-svn: 192397
2013-10-10 21:29:02 +00:00
Matthias Braun
ace00a09c8 Work on LiveRange instead of LiveInterval where possible
Also change some pointer arguments to references at some places where
0-pointers are not allowed.

llvm-svn: 192396
2013-10-10 21:28:57 +00:00
Matthias Braun
0b8a8b6641 Change MachineVerifier to work on LiveRange + LiveInterval
llvm-svn: 192395
2013-10-10 21:28:54 +00:00
Matthias Braun
0fcc48eb53 Pass LiveQueryResult by value
This makes the API a bit more natural to use and makes it easier to make
LiveRanges implementation details private.

llvm-svn: 192394
2013-10-10 21:28:52 +00:00
Matthias Braun
bcd7da9aa2 Refactor LiveInterval: introduce new LiveRange class
LiveRange just manages a list of segments and a list of value numbers
now as LiveInterval did previously, but without having details like spill
weight or a fixed register number.
LiveInterval is now a subclass of LiveRange and simply adds the spill weight
and the register number.

llvm-svn: 192393
2013-10-10 21:28:47 +00:00
Matthias Braun
63c2445abb Rename LiveRange to LiveInterval::Segment
The Segment struct contains a single interval; multiple instances of this struct
are used to construct a live range, but the struct is not a live range by
itself.

llvm-svn: 192392
2013-10-10 21:28:43 +00:00
Matthias Braun
919868389c Rename parameter: defined regs are not incoming.
llvm-svn: 192391
2013-10-10 21:28:38 +00:00
Sriram Murali
9494045fff test commit
- fix comments on vector type legalization

llvm-svn: 192389
2013-10-10 20:24:53 +00:00
Matt Arsenault
b9162d08b6 Use getPointerSizeInBits() rather than 8 * getPointerSize()
llvm-svn: 192386
2013-10-10 19:09:05 +00:00
Matt Arsenault
f7688b53a6 Fix grammar / missing words
llvm-svn: 192380
2013-10-10 18:47:35 +00:00
Manman Ren
1f6bdc7436 Debug Info: In DIBuilder, the context field of subprogram is updated to use
DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192378
2013-10-10 18:40:01 +00:00
Manman Ren
615619229d Add comments to debug info testing case.
llvm-svn: 192376
2013-10-10 18:13:17 +00:00
Matt Arsenault
6f45619203 R600: Fix trunc i64 to i32 on SI
llvm-svn: 192375
2013-10-10 18:04:16 +00:00
Hans Wennborg
01ae8115a6 Provide msbuild integration for vs2013.
Patch by Josh Samuel!

llvm-svn: 192371
2013-10-10 17:32:01 +00:00
Hans Wennborg
50851feae9 Fix msbuild integration install script.
We previously failed to check whether the SUCCESS variable was set,
and would thus always exit with a failure if vs2012 didn't exist.

llvm-svn: 192370
2013-10-10 17:31:54 +00:00
Tom Stellard
fcdfd4eca8 R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*
The function is used by the machine verifier and checks that VOP*
instructions have legal operands.

llvm-svn: 192367
2013-10-10 17:11:55 +00:00
Tom Stellard
582bb030db R600/SI: Use -verify-machineinstrs for most tests
We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192366
2013-10-10 17:11:46 +00:00
Tom Stellard
fd007665ff R600/SI: Define a separate MIMG instruction for each possible output value type
During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks.  This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.

We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.

llvm-svn: 192365
2013-10-10 17:11:24 +00:00
Tom Stellard
d407d90f9a R600/SI: Mark the EXEC register as reserved
This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192364
2013-10-10 17:11:19 +00:00
Tom Stellard
84bc464877 R600: Use StructurizeCFGPass for non SI targets
StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
shader from shadertoy (which exhibits complex control flow constructs) to works
correctly with respect to CFG handling (and allow us to detect potential bug in
other part of the backend).

We provide a cmd line argument to disable the pass for debug purpose.

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192363
2013-10-10 17:11:12 +00:00
Hao Liu
d0ab407a23 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361
2013-10-10 17:00:52 +00:00
Rafael Espindola
bb93e39fe2 Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.

llvm-svn: 192354
2013-10-10 15:15:17 +00:00
Hao Liu
0ff11c9c71 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192352
2013-10-10 15:01:24 +00:00
Benjamin Kramer
4cb23ab23b ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.
llvm-svn: 192350
2013-10-10 14:35:45 +00:00
Benjamin Kramer
11421cc493 Disable function padding to get this test to pass on atom.
llvm-svn: 192348
2013-10-10 12:46:23 +00:00
Tim Northover
50b95fa75d ARM: correct liveness flags during ARMLoadStoreOpt
When we had a sequence like:

    s1 = VLDRS [r0, 1], Q0<imp-def>
    s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
    s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
    s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>

we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.

This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.

rdar://problem/15124449

llvm-svn: 192344
2013-10-10 09:28:20 +00:00
Craig Topper
60ef08db39 Allow non-AVX form of pmovmskb to take a GR64 operand.
llvm-svn: 192341
2013-10-10 05:33:31 +00:00
Craig Topper
45f6a833a2 Remove duplicate instructions.
llvm-svn: 192340
2013-10-10 05:01:22 +00:00
Craig Topper
5478d3f8df Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
llvm-svn: 192339
2013-10-10 04:26:52 +00:00
Akira Hatanaka
d7e78a8926 [mips] Do not generate INS/EXT nodes if target does not have support for
ins/ext.

llvm-svn: 192330
2013-10-09 23:36:17 +00:00
Rui Ueyama
3d4e6c8475 Revert "llvm-c: Make target initializer functions external functions in lib."
This reverts commit r192316. The original change introduced circular
dependencies between libTarget and backends. That would broke a build unless
link everything into one big binary.

llvm-svn: 192329
2013-10-09 23:15:49 +00:00
Manman Ren
992ab551ae Debug Info: In DIBuilder, the context and type fields of template_type and
template_value are updated to use DIRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192320
2013-10-09 19:46:28 +00:00
Anders Waldenborg
d556328a9c llvm-c: Make target initializer functions external functions in lib.
Making them proper functions defined in the (shared)lib instead of
static inlines defined in the header files makes it possible to
actually distribute a binary compiled against the shared library
without having to worry about getting undefined symbol errors when
calling e.g LLVMInitializeAllTargetInfos because the shared library on
the other system was compiled with different targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D1714

llvm-svn: 192316
2013-10-09 19:02:09 +00:00
Manman Ren
25dbd15627 Debug Info: In DIBuilder, the context field of a forward decl is updated
to use DIScopeRef.

llvm-svn: 192309
2013-10-09 18:10:55 +00:00
Bill Wendling
59f3477f4f Add missing releases.
llvm-svn: 192304
2013-10-09 17:37:04 +00:00
Benjamin Kramer
2f83eef8d9 Flip the ownership of MCStreamer and MCTargetStreamer.
MCStreamer now owns the target streamer. This prevents leaking the target
streamer.

llvm-svn: 192303
2013-10-09 17:23:41 +00:00
Shuxin Yang
708f0cc2e4 Fix a bug in Dead Argument Elimination.
If a function seen at compile time is not necessarily the one linked to
the binary being built, it is illegal to change the actual arguments
passing to it. 

  e.g. 
   --------------------------
   void foo(int lol) {
     // foo() has linkage satisifying isWeakForLinker()
     // "lol" is not used at all.
   }

   void bar(int lo2) {
      // xform to foo(undef) is illegal, as compiler dose not know which
      // instance of foo() will be linked to the the binary being built.
      foo(lol2); 
   }
  -----------------------------

  Such functions can be captured by isWeakForLinker(). NOTE that
mayBeOverridden() is insufficient for this purpose as it dosen't include
linkage types like AvailableExternallyLinkage and LinkOnceODRLinkage.
Take link_odr* as an example, it indicates a set of *EQUIVALENT* globals
that can be merged at link-time. However, the semantic of 
*EQUIVALENT*-functions includes parameters. Changing parameters breaks
the assumption.

  Thank John McCall for help, especially for the explanation of subtle
difference between linkage types.

  rdar://11546243

llvm-svn: 192302
2013-10-09 17:21:44 +00:00
Rafael Espindola
f0991565b5 Add a GlobalAlias::isValidLinkage to reduce code duplication.
Thanks to Reid Kleckner for the suggestion.

llvm-svn: 192298
2013-10-09 16:07:32 +00:00
Venkatraman Govindaraju
aedc12be2e [Sparc] Disable tail call optimization for sparc64.
This patch fixes PR17506.

llvm-svn: 192294
2013-10-09 12:50:39 +00:00
Greg Bedwell
779f0d60f1 Test commit. Remove whitespace from otherwise empty lines.
llvm-svn: 192284
2013-10-09 08:55:27 +00:00
Elena Demikhovsky
f24ecf7862 AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.
llvm-svn: 192283
2013-10-09 08:16:14 +00:00
Tim Northover
87db53ff7a AArch64: enable MISched by default.
Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.

There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.

llvm-svn: 192282
2013-10-09 07:53:57 +00:00
Tim Northover
a9df6657ee AArch64: migrate ADRP relaxation test to be llvm-mc only.
llvm-svn: 192281
2013-10-09 07:53:49 +00:00
Craig Topper
36e55db0c3 More x86 disassembler filtering cleanup.
llvm-svn: 192279
2013-10-09 06:12:53 +00:00
Andrew Trick
6456fd444d Add missing HasAVX512 predicate.
This was only working because AVX had cheaper rules in all cases.
I'm sure there are other places in this file where predicates are missing.

llvm-svn: 192276
2013-10-09 05:11:10 +00:00
Craig Topper
78a2070f4a Remove some old filters from the x86 disassembler table builder.
llvm-svn: 192275
2013-10-09 05:02:29 +00:00
Craig Topper
bd2eef914f Replace a couple instructions with patterns referring to other instructions with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler.
llvm-svn: 192274
2013-10-09 04:54:21 +00:00
Craig Topper
ae27a7b281 Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v'
llvm-svn: 192272
2013-10-09 04:24:38 +00:00
Craig Topper
718df5110c Mark some instructions as CodeGenOnly since they aren't needed by the assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables.
llvm-svn: 192271
2013-10-09 03:56:16 +00:00
Craig Topper
d5082631e1 Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size.
llvm-svn: 192266
2013-10-09 02:18:34 +00:00