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7952 Commits

Author SHA1 Message Date
Dale Johannesen
6cb8a628a2 Rewrite tblgen handling of subtarget features so 
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.

llvm-svn: 47143
 2008-02-14 23:35:16 +00:00
Nate Begeman
9deedb0114 Fix single precision FP constants on SPU. They are actually legal, 
which allows us to kill a target-specific node.

llvm-svn: 47127
 2008-02-14 18:43:04 +00:00
Duncan Sands
0056f1e823 In TargetLowering::LowerCallTo, don't assert that 
the return value is zero-extended if it isn't
sign-extended.  It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned".  Currently
isSExt is set when signed, and nothing is
set otherwise.  This should be right for all
calls to standard library routines.

llvm-svn: 47122
 2008-02-14 17:28:50 +00:00
Nate Begeman
1ef1013b6c Change how FP immediates are handled. 
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.

llvm-svn: 47121
 2008-02-14 08:57:00 +00:00
Nate Begeman
5d61361bb9 Move some useful operands up into the all-targets .td 
llvm-svn: 47115
 2008-02-14 07:25:46 +00:00
Chris Lattner
b714906acf upgrade some entries, remove stuff that is done. 
llvm-svn: 47109
 2008-02-14 06:19:02 +00:00
Chris Lattner
037aa64987 the mid-level optimizer removes this stuff. 
llvm-svn: 47108
 2008-02-14 05:43:18 +00:00
Chris Lattner
10dc770a36 this one is easy. 
llvm-svn: 47107
 2008-02-14 05:41:38 +00:00
Chris Lattner
d696c25db5 This readme entry is done, testcase here: CodeGen/X86/zero-remat.ll 
llvm-svn: 47106
 2008-02-14 05:39:46 +00:00
Dan Gohman
737856bd0d Assigning an APInt to 0 with plain assignment gives it a one-bit 
size. Initialize these APInts to properly-sized zero values.

llvm-svn: 47099
 2008-02-13 23:07:24 +00:00
Dan Gohman
99b38405e3 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits 
to pass the mask APInt by value, not by reference. 

llvm-svn: 47096
 2008-02-13 22:28:48 +00:00
Nicolas Geoffray
72fa78e195 Enable exception handling int JIT 
llvm-svn: 47079
 2008-02-13 18:39:37 +00:00
Chris Lattner
80b3a56774 Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR. 
llvm-svn: 47067
 2008-02-13 17:24:14 +00:00
Chris Lattner
57f2088225 don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS. 
DAGCombine is now quite good at zapifying them.

llvm-svn: 47053
 2008-02-13 07:35:30 +00:00
Nate Begeman
5f18794295 readme updates 
llvm-svn: 47051
 2008-02-13 07:06:12 +00:00
Nate Begeman
1867c6c264 Make register scavenging happy by not using a reg (CR0) that isn't defined 
llvm-svn: 47045
 2008-02-13 02:58:33 +00:00
Evan Cheng
4b37f5ff05 commuteInstr() can now commute non-ssa machine instrs. 
llvm-svn: 47043
 2008-02-13 02:46:49 +00:00
Dan Gohman
09023887f8 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. 
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.

llvm-svn: 47039
 2008-02-13 00:35:47 +00:00
Dale Johannesen
4621e574c9 __DATA not __DATA__ is the right segment name on darwin. 
Spotted by Nick Kledzik.

llvm-svn: 47037
 2008-02-12 23:35:09 +00:00
Nate Begeman
589ecad41d Remove some dead code 
llvm-svn: 47036
 2008-02-12 22:54:40 +00:00
Nate Begeman
810b85bde8 SSE4.1 64b integer insert/extract pattern support 
Move formats into the formats file

llvm-svn: 47035
 2008-02-12 22:51:28 +00:00
Evan Cheng
b05b05aba5 Revert r46916 PPCTargetAsmInfo.cpp. 
llvm-svn: 47020
 2008-02-12 19:25:12 +00:00
Evan Cheng
e3ddcfa588 Only using x86-64 rip relative addressing in non-staic mode? 
llvm-svn: 47019
 2008-02-12 19:20:46 +00:00
Evan Cheng
c3875c88a7 Update comment. 
llvm-svn: 47002
 2008-02-12 07:59:55 +00:00
Evan Cheng
075ce702eb Unbreak various insert_vector_elt and extract_vector_elt tests in presence of SSE4. 
llvm-svn: 47001
 2008-02-12 07:59:45 +00:00
Nate Begeman
5c59b16468 Stuff noticed while grepping code 
llvm-svn: 46979
 2008-02-11 23:47:56 +00:00
Nate Begeman
5a4e290b70 Enable SSE4 codegen and pattern matching. 
Add some notes to the README.

llvm-svn: 46949
 2008-02-11 04:19:36 +00:00
Nate Begeman
9e8b2ffd52 additional missing feature 
llvm-svn: 46948
 2008-02-11 04:16:09 +00:00
Nate Begeman
297d683980 xmm0 variable blends 
llvm-svn: 46931
 2008-02-10 18:47:57 +00:00
Dan Gohman
cabaec582f Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00
Nick Lewycky
b072c0b3ed Match GCC's behaviour for these sections. 
llvm-svn: 46916
 2008-02-10 00:03:54 +00:00
Nate Begeman
2627ffd14b memopv16i8 had wrong alignment requirement, would have broken pabsb 
pabs{b,w,d} are not two address
fix extract-to-mem sse4 ops
add sse4 vector sign extend nodes

llvm-svn: 46915
 2008-02-09 23:46:37 +00:00
Nate Begeman
a78c35a368 Skeleton of insert and extract matching, more to come 
llvm-svn: 46902
 2008-02-09 01:38:08 +00:00
Nate Begeman
336fba2146 Tablegen support for insert & extract element matching 
llvm-svn: 46901
 2008-02-09 01:37:05 +00:00
Evan Cheng
90f03a0b88 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 
llvm-svn: 46893
 2008-02-08 21:20:40 +00:00
Dale Johannesen
9bbfeaea4d 64-bit (MMX) vectors do not need restrictive alignment. 
128-bit vectors need it only when SSE is on.

llvm-svn: 46890
 2008-02-08 19:48:20 +00:00
Dan Gohman
d1cc100aef Avoid needlessly casting away const qualifiers. 
llvm-svn: 46877
 2008-02-08 03:29:40 +00:00
Evan Cheng
b2bc19ee5b Added missing entries in X86 load / store folding tables. 
llvm-svn: 46866
 2008-02-08 00:12:56 +00:00
Dan Gohman
eb7c8e4f6b Follow Chris' suggestion; change the PseudoSourceValue accessors 
to return pointers instead of references, since this is always what
is needed.

llvm-svn: 46857
 2008-02-07 18:41:25 +00:00
Dan Gohman
3af6eba3dd Add SourceValue information for outgoing argument stores on x86. 
llvm-svn: 46854
 2008-02-07 16:28:05 +00:00
Evan Cheng
a377b2bbd1 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. 
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax

llvm-svn: 46850
 2008-02-07 08:53:49 +00:00
Evan Cheng
92635b3d94 In some cases, e.g. ADD32ri, no transformation is made. Guide against it. 
llvm-svn: 46849
 2008-02-07 08:29:53 +00:00
Dan Gohman
f00842e086 Re-apply the memory operand changes, with a fix for the static 
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.

llvm-svn: 46827
 2008-02-06 22:27:42 +00:00
Evan Cheng
e509232483 Move to getCALLSEQ_END to ensure CALLSEQ_END node produces a flag. This is consistent with the definition in td file. 
llvm-svn: 46775
 2008-02-05 22:44:06 +00:00
Dale Johannesen
e8fa3130f8 Implement sseregparm. 
llvm-svn: 46764
 2008-02-05 20:46:33 +00:00
Nate Begeman
9f4245c16a Ident mnemonics appropriately 
llvm-svn: 46746
 2008-02-05 08:49:09 +00:00
Evan Cheng
1c67dcaae7 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. 
llvm-svn: 46724
 2008-02-04 23:06:48 +00:00
Nate Begeman
2b00217d58 This method should be virtual 
llvm-svn: 46723
 2008-02-04 23:04:24 +00:00
Nate Begeman
8285430ed7 Eliminate some redundant code. 
llvm-svn: 46720
 2008-02-04 21:44:06 +00:00
Nate Begeman
16830a34c4 The rest of the SSE4.1 intrinsic patterns that are obvious to me. Getting 
Evan's help with the rest.

llvm-svn: 46697
 2008-02-04 06:00:24 +00:00