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Commit Graph

200009 Commits

Author SHA1 Message Date
Matt Arsenault
3ca73de82f AMDGPU/GlobalISel: Add baseline add/sub sat legalization tests 2020-07-13 14:46:40 -04:00
Lei Zhang
767650cdb4 [NFC] Remove unused header include
Differential Revision: https://reviews.llvm.org/D83706
2020-07-13 14:43:48 -04:00
serge-sans-paille
568fbc4c30 Fix HexagonGenExtract return status
Differential Revision: https://reviews.llvm.org/D83460
2020-07-13 20:41:59 +02:00
Arthur Eubanks
084b730605 [NewPM][opt] Translate -foo-analysis to require<foo-analysis>
Fixes 53 check-llvm tests under NPM.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D83633
2020-07-13 11:24:59 -07:00
LLVM GN Syncbot
9485ea1e41 [gn build] Port fdb69539bcd 2020-07-13 18:10:37 +00:00
Matt Arsenault
7d05717276 AMDGPU/GlobalISel: Add tests for 96-bit add/sub/mul
I almost regressed these, so add tests for them.
2020-07-13 14:07:34 -04:00
Mircea Trofin
d25cc6a592 [llvm][NFC] ML Policies: changed the saved_model protobuf to text
Also compacted the checkpoints (variables) to one file (plus the index).

This reduces the binary model files to just the variables and their
index. The index is very small. The variables are serialized float
arrays. When updated through training, the changes are very likely
unlocalized, so there's very little value in them being anything else
than binary.
2020-07-13 11:07:07 -07:00
Matt Arsenault
de32382a70 TableGen/GlobalISel: Emit enum names for reg class ID instead of value
This was emitting the raw value for the reg class ID with a comment
for the actual class name. Switch to emitting the qualified enum name
instead, which obviates the need for the comment and also helps keep
the lit tests on the emitter output more stable.
2020-07-13 14:02:08 -04:00
Matt Arsenault
1ee52b6300 RISCV: Avoid GlobalISel build break in a future patch
The GlobalISelEmitter is stricter about matching timm instruction
outputs to timm inputs (although in an accidental sort of way that
doesn't hit a proper import failure error). Also, apparently no
intrinsic patterns were importing since the ID enum declaration was
missing.
2020-07-13 14:01:57 -04:00
Hiroshi Yamauchi
5983590127 [PGO][PGSO] Add profile guided size optimization to X86ISelDAGToDAG.
Differential Revision: https://reviews.llvm.org/D83331
2020-07-13 10:28:09 -07:00
LLVM GN Syncbot
4289f3f3ad [gn build] Port 83080a294ad 2020-07-13 17:19:05 +00:00
Lang Hames
be5f814275 [ORC] Generalize emit re-entry, stub, etc. APIs for working addr != link addr.
This patch generalizes the APIs for writing re-entry blocks, trampolines and
stubs to allow their final linked address to differ from the address of
their initial working memory. This will allow these routines to be used with
JITLinkMemoryManagers, which will in turn allow for unification of code paths
for in-process and cross-process lazy JITing.
2020-07-13 10:15:10 -07:00
Lang Hames
e88280801b [JITLink] Add a synchronous version of finalize for convenience.
This will be used by upcoming patches that implement indirection utils
(reentry, reentry trampolines, and stubs) on top of
JITLinkMemoryManager to unify in-process and cross-process lazy
compilation support.
2020-07-13 10:15:10 -07:00
Mircea Trofin
f77d61cf7b [llvm] Native size estimator for training -Oz inliner
Summary:
This is an experimental ML-based native size estimator, necessary for
computing partial rewards during -Oz inliner policy training. Data
extraction for model training will be provided in a separate patch.

RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140763.html

Reviewers: davidxl, jdoerfert

Subscribers: mgorny, hiraditya, mgrang, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82817
2020-07-13 10:13:56 -07:00
Hiroshi Yamauchi
e525e00307 [PGO][PGSO] Add profile guided size optimization to the X86 LEA fixup.
Differential Revision: https://reviews.llvm.org/D83330
2020-07-13 09:46:22 -07:00
Sanjay Patel
68e3493e48 [DAGCombiner] rot i16 X, 8 --> bswap X
We have this generic transform in IR (instcombine),
but as shown in PR41098:
http://bugs.llvm.org/PR41098
...the pattern may emerge in codegen too.

x86 has a potential refinement/reversal opportunity here,
but that should come later or needs a target hook to
avoid the transform. Converting to bswap is the more
specific form, so we should use it if it is available.
2020-07-13 12:01:53 -04:00
Sanjay Patel
217126ba1d [x86] add tests for bswap/rotate; NFC 2020-07-13 12:01:53 -04:00
Pavel Iliin
5410e8da94 [ARM][NFC] More detailed vbsl checks in ARM & Thumb2 tests. 2020-07-13 17:00:43 +01:00
stevewan
f1312423ac [llvm-ar][test][AIX] Unsupport error-opening-directory.test on AIX
Summary:
The test fails on AIX as it allows open() and read() on a directory. This patch adds `# UNSUPPORTED:
system-aix` to the test to prevent it from running on AIX.

Reviewers: sameerarora101, daltenty, ShuhongL, hubert.reinterpretcast, MaskRay, smeenai, alexshap

Reviewed By: sameerarora101, hubert.reinterpretcast, MaskRay, smeenai

Subscribers: MaskRay, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83579
2020-07-13 12:00:07 -04:00
Pavel Labath
af4f8a5640 [ADT] Make Load(AP)IntFromMemory pointer argument const
The function does not modify this memory.
2020-07-13 17:32:54 +02:00
Sanne Wouda
7ff41afc34 Fix llvm-test-suite failure introduced by D82550/D83122
Apparently, isIndirectCall does not imply that getCalledFunction will be non-null
2020-07-13 16:14:22 +01:00
Eric Astor
674dcb3af4 [ms] [llvm-ml] Restore omitted changes requested by reviewer 2020-07-13 10:49:19 -04:00
Eric Astor
15ff35309f [ms] [llvm-ml] Add support for MASM STRUCT casting field accessors: (<TYPE> PTR <value>).<field>
Summary:
Add support for MASM STRUCT casting field accessors: (<TYPE> PTR <value>).<field>

Since these are operands, we add them to X86AsmParser. If/when we extend MASM support to other architectures (e.g., ARM), we will need similar changes there as well.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D83346
2020-07-13 10:40:47 -04:00
Jinsong Ji
230bde0625 [compiler-rt][CMake] Pass down LLVM_LIT_ARGS in runtime build
We should also pass down the LLVM_LIT_ARGS in runtime build mode,
so that the runtime tests can be well controlled as well.

We actually passed this down in clang/runtime/CMakeLists.txt
But not for calls from llvm/runtime/CMakeLists.txt.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D83565
2020-07-13 14:38:06 +00:00
Eric Astor
1c2f9b3ec9 [ms] [llvm-ml] Fix MASM support for nested unnamed STRUCTs and UNIONs
Summary: Fix MASM support for nested unnamed STRUCTs and UNIONs

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D83345
2020-07-13 10:36:56 -04:00
Eric Astor
a4b0bd1d7d [ms] [llvm-ml] Improve MASM STRUCT field accessor support
Summary:
Adds support for several accessors:
- `[<identifier>.<struct name>].<field>`
- `[<identifier>.<struct name>.<field>].<subfield>` (where `field` has already-defined STRUCT type)
- `[<variable>.<field>].<subfield>` (where `field` has already-defined STRUCT type)

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D83344
2020-07-13 10:34:30 -04:00
Sanne Wouda
d79de12ea6 [NFC] rename to reflect F is not necessarily an Intrinsic 2020-07-13 15:28:46 +01:00
Sanne Wouda
a003603bd6 [SLPVectorizer] handle vectorizeable library functions
Teaches the SLPVectorizer to use vectorized library functions for
non-intrinsic calls.

This already worked for intrinsics that have vectorized library
functions, thanks to D75878, but schedules with library functions with a
vector variant were being rejected early.

-   assume that there are no load/store dependencies between lib
    functions with a vector variant; this would otherwise prevent the
    bundle from becoming "ready"

-   check during legalization that the vector variant can be used

-   fix-up where we previously assumed that a call would be an intrinsic

Differential Revision: https://reviews.llvm.org/D82550
2020-07-13 15:28:46 +01:00
Sanne Wouda
93bdebae6d Pre-commit tests
Prepare to land D82550
2020-07-13 15:28:46 +01:00
Sanne Wouda
7ed97c8065 Fix crash when getVFABIMappings is called with an indirect call instruction
Differential Revision: https://reviews.llvm.org/D83122
2020-07-13 15:28:46 +01:00
Georgii Rymar
cf9e8f01e5 [yaml2obj] - Refactor header-sh-fields.yaml test.
This refines the test to use macros. It is needed for
a follow-up change that adds a functionality to
override more fields.

Also, it is just cleaner to test each key separately.

Differential revision: https://reviews.llvm.org/D83481
2020-07-13 16:12:22 +03:00
Sanjay Patel
e6d4089b0d [DAGCombiner] allow load/store merging if pairs can be rotated into place
This carves out an exception for a pair of consecutive loads that are
reversed from the consecutive order of a pair of stores. All of the
existing profitability/legality checks for the memops remain between
the 2 altered hunks of code.

This should give us the same x86 base-case asm that gcc gets in
PR41098 and PR44895:
http://bugs.llvm.org/PR41098
http://bugs.llvm.org/PR44895

I think we are missing a potential subsequent conversion to use "movbe"
if the target supports that. That might be similar to what AArch64
would use to get "rev16".

Differential Revision: https://reviews.llvm.org/D83567
2020-07-13 08:57:00 -04:00
Sanjay Patel
86d4edf021 Revert "[DAGCombiner] allow load/store merging if pairs can be rotated into place"
This reverts commit 591a3af5c7acc05617c0eacf6ae4f76bd8a9a6ce.
The commit message was cut off and failed to include the review citation.
2020-07-13 08:55:29 -04:00
Sanjay Patel
37cf92de0a [DAGCombiner] allow load/store merging if pairs can be rotated into place
This carves out an exception for a pair of consecutive loads that are
reversed from the consecutive order of a pair of stores. All of the
existing profitability/legality checks for the memops remain between
the 2 altered hunks of code.

This should give us the same x86 base-case asm that gcc gets in
PR41098 and PR44895:i
http://bugs.llvm.org/PR41098
http://bugs.llvm.org/PR44895

I think we are missing a potential subsequent conversion to use "movbe"
if the target supports that. That might be similar to what AArch64
would use to get "rev16".

Differential Revision:
2020-07-13 08:53:06 -04:00
Sjoerd Meijer
ad0b9a0feb [ARM][MVE] Refactor option -disable-mve-tail-predication
This refactors option -disable-mve-tail-predication to take different arguments
so that we have 1 option to control tail-predication rather than several
different ones.

This is also a prep step for D82953, in which we want to reject reductions
unless that is requested with this option.

Differential Revision: https://reviews.llvm.org/D83133
2020-07-13 13:40:33 +01:00
Mirko Brkusanin
5869dbd86c [AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot.
Temporarily remove subregister for EXEC in selectBallot added in
https://reviews.llvm.org/D83214 to fix failures on expensive checks buildbot.
2020-07-13 13:35:34 +02:00
Georgii Rymar
e9920e279f [llvm-readobj] - Add a generic test for --dyn-relocations and fix an issue.
We have an issue currently: --dyn-relocations always prints the following
relocation header when dumping `DynPLTRelRegion`:

"Offset  Info  Type Symbol's Value  Symbol's Name + Addend"

I.e. even for an empty object, --dyn-relocations still prints this.
It is a easy to fix bug, but we have no dedicated test case for this option.
(we have a dynamic-reloc-no-section-headers.test, which has a slightly different purpose).

This patch adds a test and fixes the behavior.

Differential revision: https://reviews.llvm.org/D83387
2020-07-13 14:22:03 +03:00
Paul Walker
bb7b8a1764 [SVE] Ensure fixed length vector fptrunc operations bigger than NEON are not considered legal.
Differential Revision: https://reviews.llvm.org/D83568
2020-07-13 11:16:30 +00:00
Mirko Brkusanin
e16295d0d1 [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
Select ballot intrinsic for GlobalISel.

Differential Revision: https://reviews.llvm.org/D83214
2020-07-13 12:14:43 +02:00
Kerry McLaughlin
3ffd2eeadb [SVE][Codegen] Add a helper function for pointer increment logic
Summary:
Helper used when splitting load & store operations to calculate
the pointer + offset for the high half of the split

Reviewers: efriedma, sdesmalen, david-arm

Reviewed By: efriedma

Subscribers: tschuett, hiraditya, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83577
2020-07-13 10:53:40 +01:00
Petar Avramovic
d6083a3a5f [GlobalISel][InlineAsm] Fix buildCopy for inputs
Check that input size matches size of destination reg class.
Attempt to extend input size when needed.

Differential Revision: https://reviews.llvm.org/D83384
2020-07-13 10:52:33 +02:00
Max Kazantsev
8b8962aa1f [InstCombine] Improve select -> phi canonicalization: consider more blocks
We can try to replace select with a Phi not in its parent block alone,
but also in blocks of its arguments. We benefit from it when select's
argument is a Phi.

Differential Revision: https://reviews.llvm.org/D83284
Reviewed By: nikic
2020-07-13 11:40:32 +07:00
Kai Luo
a7930d8f42 [PowerPC] Enhance tests for D83276. NFC. 2020-07-13 04:37:09 +00:00
Qiu Chaofan
e2a03586ce [PowerPC] Support constrained conversion in SPE target
This patch adds support for constrained int/fp conversion between
signed/unsigned i32 and f32/f64.

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D82747
2020-07-13 12:18:36 +08:00
Fangrui Song
d6b47fd073 [MC][RISCV] Set UseIntegratedAssembler to true
to align with most other targets. Also, -fintegrated-as is the default
for clang -target riscv*.
2020-07-12 21:04:48 -07:00
Atmn Patel
d9fbe44816 [OpenMP] Add firstprivate as a default data-sharing attribute to clang
This implements the default(firstprivate) clause as defined in OpenMP
Technical Report 8 (2.22.4).

Reviewed By: jdoerfert, ABataev

Differential Revision: https://reviews.llvm.org/D75591
2020-07-12 23:01:40 -05:00
Craig Topper
dfa82a9f2e [X86] Rename X86_CPU_TYPE_COMPAT_ALIAS/X86_CPU_TYPE_COMPAT/X86_CPU_SUBTYPE_COMPAT macros. NFC
Remove _COMPAT. Drop the ARCHNAME. Remove the non-COMPAT versions
that are no longer needed.

We now only use these macros in places where we need compatibility
with libgcc/compiler-rt. So we don't need to call out _COMPAT
specifically.
2020-07-12 17:00:24 -07:00
Shinji Okumura
3ac326f3a6 [Attributor] Add AAValueSimplifyCallSiteArgument::manifest
Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D82861
2020-07-13 07:01:50 +09:00
Alexey Lapshin
3ab8085c21 Revert "[TRE] allow TRE for non-capturing calls."
This reverts commit f7907e9d223d8484f9afd457ba614c2db2ae4743.

That commit caused error on multi-stage build.
2020-07-13 00:39:48 +03:00
Craig Topper
0f92e7936c [X86] Remove model number based detection for 'pentiumpro', 'pentium2', 'pentium3', 'pentium-m', and 'yonah' from getHostCPUName.
For model 6 CPUs, we have a fallback detection method based on
available features. That mechanism should be enough to detect
these early family 6 CPUs as they only differ in the features
used by the detection anyway.
2020-07-12 12:59:25 -07:00