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80 Commits

Author SHA1 Message Date
Jia Liu
6bb2f0f0e4 some comment fix for X86 and ARM 
llvm-svn: 150902
 2012-02-19 02:03:36 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Craig Topper
c9756440ea Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget. 
llvm-svn: 147841
 2012-01-10 06:30:56 +00:00
Craig Topper
3fb8201fcb Enable FISTTP* instructions when AVX is enabled. 
llvm-svn: 147758
 2012-01-08 23:04:21 +00:00
Devang Patel
131611237d Intel style asm variant does not need '%' prefix. 
llvm-svn: 147453
 2012-01-03 18:22:10 +00:00
Jakob Stoklund Olesen
7d3e1553d2 Clean up the handling of the x87 fp stack to make it more robust. 
Drop the FpMov instructions, use plain COPY instead.

Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.

This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.

As a bonus we handle floating point inline assembly correctly now.

llvm-svn: 134018
 2011-06-28 18:32:28 +00:00
Reid Kleckner
0e68b2ed88 Add encodings and mnemonics for FXSAVE64 and FXRSTOR64. 
These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.

llvm-svn: 125446
 2011-02-12 23:24:13 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Eric Christopher
3a1c712e47 Move X86InstrFPStack.td over to PseudoI as well. 
llvm-svn: 120470
 2010-11-30 21:57:32 +00:00
Chris Lattner
0d6d870628 go to great lengths to work around a GAS bug my previous patch 
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356
 2010-11-06 21:37:06 +00:00
Chris Lattner
af1f50772a change the fp comparison instructions to not have %st0 explicitly 
listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354
 2010-11-06 20:55:09 +00:00
Andrew Trick
b9e8700beb Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Kevin Enderby
c63105a064 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Chris Lattner
12274b9845 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719
 2010-10-05 23:58:18 +00:00
Chris Lattner
db65ba5acf refactor .td files a bit, moving system instructions out to X86InstrSystem.td 
llvm-svn: 115591
 2010-10-05 05:32:15 +00:00
Chris Lattner
c81dcbec9e convert the last 4 X86ISD nodes that should have memoperands to have them. 
llvm-svn: 114523
 2010-09-22 01:28:21 +00:00
Chris Lattner
fee1ac61bd give FP_TO_INT16_IN_MEM and friends a memoperand. They are only 
used with stack slots, but hey, lets be safe.

llvm-svn: 114521
 2010-09-22 01:05:16 +00:00
Bob Wilson
640cc8ce83 Fix comment typos. 
llvm-svn: 112202
 2010-08-26 18:08:11 +00:00
Jakob Stoklund Olesen
858d6bb512 Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill 
pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536
 2010-07-16 17:41:44 +00:00
Jakob Stoklund Olesen
73e71c4703 Use target independent COPY instructions for the fake fextend and fround 
operations in x87 code.

llvm-svn: 108098
 2010-07-11 18:19:39 +00:00
Eric Christopher
e0cc8e131e Remove isTwoAddress from here too. 
llvm-svn: 106358
 2010-06-18 23:56:07 +00:00
Kevin Enderby
ce7a24a57f Changed llvm-mc to use the same suffixes with floating point compare 
instructions as the Mac OS X darwin assembler.  Some of which like 'fcoml'
assembled to different opcodes.  While some of the suffixes were just different.

llvm-svn: 102958
 2010-05-03 21:31:40 +00:00
Chris Lattner
938747fc7f Now that tblgen can handle matching implicit defs of instructions 
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903
 2010-03-19 00:01:11 +00:00
Chris Lattner
1469c1b01e add support for pentium class CPUs which do not have cmov, 
PR4841.  Patch by Craig Smith!

llvm-svn: 98496
 2010-03-14 18:31:44 +00:00
Dan Gohman
99c6bcbc13 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Chris Lattner
9d4e878b6a fix a case where we'd mis-encode fisttp because of an incorrect (and 
redundant with a correct one) pattern that was added for the disassembler.

llvm-svn: 95446
 2010-02-05 22:49:06 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Sean Callanan
e482e93995 Removed a few instructions that were already 
covered by other definitions.

llvm-svn: 81992
 2009-09-16 01:54:38 +00:00
Sean Callanan
296ed7d1e1 Added a variety of floating-point and SSE instructions. 
All of these do not have patterns (they're for the
disassembler).

Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs.  So I put them
together and left a comment.

llvm-svn: 81979
 2009-09-16 01:13:52 +00:00
Evan Cheng
3b84024598 Implement FpSET_ST1_*. 
llvm-svn: 64186
 2009-02-09 23:32:07 +00:00
Dan Gohman
5dad0993a9 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Dale Johannesen
8c1e95810f Use ## for comment delimiter on darwin x86-32, so 
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors.  Approach
suggested by Daveed Vandevoorde.

llvm-svn: 48808
 2008-03-25 23:29:30 +00:00
Chris Lattner
edfc239ced remove Evan's "ugly hack" that sorta attempted to get 
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.

llvm-svn: 48635
 2008-03-21 06:50:21 +00:00
Chris Lattner
8a4fa95cae Add support for calls that return two FP values in 
ST(0)/ST(1).

llvm-svn: 48634
 2008-03-21 06:38:26 +00:00
Chris Lattner
d393772580 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to 
copyfromreg/copytoreg instead.

llvm-svn: 48174
 2008-03-10 21:08:41 +00:00
Chris Lattner
2e7537b60b rename FP_SETRESULT -> FP_SET_ST0 
llvm-svn: 48094
 2008-03-09 07:08:44 +00:00
Chris Lattner
826402e365 rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for 
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.

llvm-svn: 48093
 2008-03-09 07:05:32 +00:00
Evan Cheng
618761903d Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results. 
Status: This only works for direct calls, and only the caller side is done. Disabled for now.

llvm-svn: 46527
 2008-01-29 19:34:22 +00:00
Chris Lattner
20d1e419b3 more flags set right 
llvm-svn: 45860
 2008-01-11 07:18:17 +00:00
Chris Lattner
9d7971791b Start inferring side effect information more aggressively, and fix many bugs in the 
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829
 2008-01-10 07:59:24 +00:00
Chris Lattner
6ad01a9965 remove explicit sets of 'neverHasSideEffects' that can now be 
inferred from the instr patterns.

llvm-svn: 45824
 2008-01-10 05:45:39 +00:00
Chris Lattner
9b4f2b2316 get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Bill Wendling
e5af8b6e5c Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I 
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.

llvm-svn: 45132
 2007-12-17 23:07:56 +00:00
Bill Wendling
b33d6155da LD_Fp64m should have "isRematerializable" set. 
llvm-svn: 45128
 2007-12-17 22:17:14 +00:00
Anton Korobeynikov
cd9b16df61 Implement codegen for flt_rounds on x86 
llvm-svn: 44183
 2007-11-16 01:31:51 +00:00
Arnold Schwaighofer
6bcd9e7ec2 Corrected many typing errors. And removed 'nest' parameter handling 
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934
 2007-10-12 21:30:57 +00:00
Evan Cheng
f3c130a8b6 Enabling new condition code modeling scheme. 
llvm-svn: 42459
 2007-09-29 00:00:36 +00:00