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Author SHA1 Message Date
Sirish Pande
086c13aed8 Make sure new value jump is enabled for Hexagon V5 as well. 
llvm-svn: 156700
 2012-05-12 05:54:15 +00:00
Sirish Pande
2eadb696a5 Support for Hexagon feature, New Value Jump. 
llvm-svn: 156698
 2012-05-12 05:10:30 +00:00
Akira Hatanaka
a80ec224bf Fix test cases. 
llvm-svn: 156697
 2012-05-12 03:25:16 +00:00
Akira Hatanaka
6d994087f3 Remove MipsEmitGPRestore.cpp. 
llvm-svn: 156696
 2012-05-12 03:24:03 +00:00
Akira Hatanaka
35fe399b7f Delete all functions that are no longer needed in MipsFunctionInfo, including 
the ones that get or set the frame index for the $gp save slot. 

Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns
GP. This function should always return a virtual register.

llvm-svn: 156695
 2012-05-12 03:22:13 +00:00
Akira Hatanaka
5aa9429fab Stop reserving register $gp. Do not call isGPFI to check whether a frame object 
is the $gp save slot.

llvm-svn: 156694
 2012-05-12 03:21:18 +00:00
Akira Hatanaka
94b61aa028 Do not add the pass which restores $gp after every function call. 
llvm-svn: 156693
 2012-05-12 03:19:51 +00:00
Akira Hatanaka
ae43b7da61 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
 2012-05-12 03:19:04 +00:00
Akira Hatanaka
f6e9e7cbc7 Make the following changes in MipsFrameLowering.cpp: 
- Stop emitting instructions needed to initialize the global pointer register.
- Stop emitting .cprestore directive.
- Do not take into account the $gp save slot when computing stack size.

llvm-svn: 156691
 2012-05-12 03:18:00 +00:00
Jakob Stoklund Olesen
afe973fad4 Speed up computeComposites() by using the new SubReg -> SubIdx map. 
TableGen doesn't need to search through the SubRegs map to find an
inverse entry.

llvm-svn: 156690
 2012-05-12 02:02:26 +00:00
Akira Hatanaka
431ee824c6 Make the following changes in MipsAsmPrinter.cpp: 
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689
 2012-05-12 00:48:43 +00:00
Chad Rosier
f276b2009c Hoist simpler checks above llvm::PointerMayBeCaptured. No functional change intended. 
llvm-svn: 156687
 2012-05-12 00:43:40 +00:00
Jakob Stoklund Olesen
aff911c34c Don't look for empty live ranges in the unions. 
Empty live ranges represent undef and still get allocated, but they
won't appear in LiveIntervalUnions.

Patch by Patrik Hägglund!

llvm-svn: 156685
 2012-05-12 00:33:28 +00:00
Akira Hatanaka
bc52a1662b Insert instructions to the entry basic block which initializes the global 
pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

llvm-svn: 156671
 2012-05-12 00:17:17 +00:00
Michael J. Spencer
ca721ac5bf Add doxygen comments. 
llvm-svn: 156665
 2012-05-11 23:34:39 +00:00
Akira Hatanaka
3e39081c4a Do not replace operands of pseudo instructions with register $zero. 
llvm-svn: 156663
 2012-05-11 23:22:18 +00:00
Chad Rosier
dba9908c4b Revert 156658. 
llvm-svn: 156662
 2012-05-11 23:21:01 +00:00
Chad Rosier
20f6e62e43 [fast-isel] Fast-isel doesn't use the expect intrinsic. 
llvm-svn: 156658
 2012-05-11 23:10:58 +00:00
Akira Hatanaka
d81273be58 Use regular expression to match register names. 
llvm-svn: 156656
 2012-05-11 23:00:40 +00:00
Bill Wendling
9c0a4581e4 Make the URL a link instead. 
llvm-svn: 156655
 2012-05-11 22:38:33 +00:00
Michael J. Spencer
6161587c9f [Support/StringRef] Add find_last_not_of and {r,l,}trim. 
llvm-svn: 156652
 2012-05-11 22:08:50 +00:00
Bill Wendling
55c91b69ec Remove extraneous ; and the resulting warning. 
llvm-svn: 156649
 2012-05-11 21:56:04 +00:00
Bill Wendling
e349cbad11 Add mention of Glasgow Haskell Compiler. 
llvm-svn: 156648
 2012-05-11 21:42:37 +00:00
Chad Rosier
4a65a2a197 [fast-isel] Add support for selecting @llvm.trap(). 
llvm-svn: 156646
 2012-05-11 21:33:49 +00:00
Brendon Cahoon
ea214cd0af Updated instruction table due to addded intrinsics. 
llvm-svn: 156644
 2012-05-11 21:10:16 +00:00
Sirish Pande
d0570c5bdd Remove warnings from HexagonVLIWPacketizer. 
llvm-svn: 156636
 2012-05-11 20:00:34 +00:00
Duncan Sands
a97949f6c4 Some release notes for dragonegg. 
llvm-svn: 156635
 2012-05-11 19:59:43 +00:00
Brendon Cahoon
90dddafa44 Hexagon constant extender support. 
Patch by Jyotsna Verma.

llvm-svn: 156634
 2012-05-11 19:56:59 +00:00
Chad Rosier
4141fa486f Typo. 
llvm-svn: 156633
 2012-05-11 19:43:29 +00:00
Chad Rosier
72bd34ca71 [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup. 
llvm-svn: 156632
 2012-05-11 19:40:25 +00:00
Sirish Pande
4590b341e2 Hexagon V5 intrinsics support. 
llvm-svn: 156631
 2012-05-11 19:39:13 +00:00
Jakob Stoklund Olesen
041239982f Defer computation of SuperRegs. 
Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

llvm-svn: 156629
 2012-05-11 19:01:01 +00:00
Chad Rosier
c20de37076 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg 
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796

llvm-svn: 156628
 2012-05-11 18:51:55 +00:00
Nuno Lopes
11d6ecb6db objectsize: add a few more tests and fix a bug 
llvm-svn: 156625
 2012-05-11 18:25:29 +00:00
Chad Rosier
4c5904bbe5 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back 
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796

llvm-svn: 156622
 2012-05-11 17:41:06 +00:00
Chad Rosier
5d178a402f The return type is an unsigned, not a bool. 
llvm-svn: 156621
 2012-05-11 16:41:38 +00:00
Manman Ren
9c31a160a8 Add space before an open parenthesis in control flow statements. 
llvm-svn: 156620
 2012-05-11 15:36:46 +00:00
Preston Gurd
691d5f1eb6 Added X86 Atom latencies to X86InstrMMX.td. 
llvm-svn: 156615
 2012-05-11 14:27:12 +00:00
Stepan Dyatkovskiy
a1652c65c7 PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support. 
llvm-svn: 156613
 2012-05-11 10:34:23 +00:00
Hans Wennborg
ea694231ad Fix test/CodeGen/X86/tls-pie.ll. 
llvm-svn: 156612
 2012-05-11 10:19:54 +00:00
Hans Wennborg
a5a417fcd3 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

llvm-svn: 156611
 2012-05-11 10:11:01 +00:00
Silviu Baranga
5138c169b1 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. 
llvm-svn: 156609
 2012-05-11 09:28:27 +00:00
Silviu Baranga
dad5ffc779 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
llvm-svn: 156608
 2012-05-11 09:10:54 +00:00
Rafael Espindola
b550a4f952 Fix a use after free when the streamer is destroyed. Fixes pr12622. 
llvm-svn: 156606
 2012-05-11 03:42:13 +00:00
Akira Hatanaka
e579470749 Fix a misleading comment. 
llvm-svn: 156603
 2012-05-11 01:45:15 +00:00
Jim Grosbach
289783c78d Tidy up. Trailing whitespace. 
llvm-svn: 156602
 2012-05-11 01:41:30 +00:00
Jim Grosbach
f588df5936 Tidy up. Trailing whitespace. 
llvm-svn: 156601
 2012-05-11 01:39:13 +00:00
Eli Friedman
1746bfc50e Fix a minor logic mistake transforming compares in instcombine. PR12514. 
llvm-svn: 156600
 2012-05-11 01:32:59 +00:00
Manman Ren
c82d0e71b9 ARM: peephole optimization to remove cmp instruction 
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411
llvm-svn: 156599
 2012-05-11 01:30:47 +00:00
Dan Gohman
ed475ad173 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), 
but it generates int3 on x86 instead of ud2.

llvm-svn: 156593
 2012-05-11 00:19:32 +00:00