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1826 Commits

Author SHA1 Message Date
Akira Hatanaka
3e7c555daa [mips] Rename DSPRegs. 
llvm-svn: 188342
 2013-08-14 00:53:38 +00:00
Akira Hatanaka
6ac16b554b [mips] Rename HIRegs and LORegs. 
llvm-svn: 188341
 2013-08-14 00:47:08 +00:00
Akira Hatanaka
ff296075bc [mips] Properly parse registers that appear in inline-asm constraints. 
llvm-svn: 188336
 2013-08-14 00:21:25 +00:00
Jack Carter
da7e928e92 [Mips][msa] Added initial MSA support. 
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
 2013-08-13 20:54:07 +00:00
Jack Carter
cb8856c2c6 [Mips] Support for unaligned load/store microMips instructions 
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
 2013-08-13 20:19:16 +00:00
Vladimir Medic
c797d9a921 This patch introduces changes to MipsAsmParser register parsing routines. The code now follows more deterministic path and makes the code more efficient and easier to maintain. 
llvm-svn: 188264
 2013-08-13 13:07:09 +00:00
Vladimir Medic
34aca92bce This patch implements ei and di instructions for mips. Test cases are added. 
llvm-svn: 188176
 2013-08-12 13:07:23 +00:00
Benjamin Kramer
01f2d8daf8 Remove global construction. const char* is sufficient here. 
No functionality change.

llvm-svn: 188158
 2013-08-12 09:37:29 +00:00
Reed Kotler
31da848d63 Don't generate floating point stubs for mips16 code if the function 
is actually an instrinsic that will not occur in libc. This list here
is not exhaustive but fixes the one places in test-suite where this occurs.
I have filed a bug against myself to research the full list and add them
to the array of such cases. In the future, actual stub generation will occur
in a later phase and we won't need this code because we will know at that time
during the compilation that in fact no helper function was even needed.

llvm-svn: 188149
 2013-08-11 21:30:27 +00:00
Reed Kotler
9508f238aa Incorrect JAL instruction attributes caused the optimizer to make a wrong 
instruction move. Just affects static relocation. -static works fine now
with mips16 for the most part.

llvm-svn: 188143
 2013-08-10 22:18:22 +00:00
Reed Kotler
d4cb39c73a Add another intrinsic that LLVM gives an incorrect prototype to. 
I need to go through all the runtime routine list and see if there
are any more I need to add for mips16 floating point. Prototypes must
be correct or else I don't know to add a helper function call.

llvm-svn: 188106
 2013-08-09 21:33:41 +00:00
Jack Carter
69e05b321a Mips ELF: MicroMips direct object Little endian support. 
Test included.

Patch by Zoran Jovanovich

llvm-svn: 188024
 2013-08-08 23:30:40 +00:00
Akira Hatanaka
c05b5c3dae [mips] Rename accumulator register classes and FP register operands. 
llvm-svn: 188020
 2013-08-08 21:54:26 +00:00
Akira Hatanaka
41ad5610bf [mips] Mark pseudo instructions as code-gen only. 
llvm-svn: 188017
 2013-08-08 21:44:39 +00:00
Akira Hatanaka
4f90298c6e [mips] Delete register class HWRegs64. 
No functionality change.

llvm-svn: 188016
 2013-08-08 21:37:32 +00:00
Reed Kotler
30cf33a57e Create a pattern for the "trap" instruction. 
llvm-svn: 187863
 2013-08-07 04:00:26 +00:00
David Blaikie
28f73e40bf Remove unused functions introduced in r172685 to unbreak the Clang -Werror build 
llvm-svn: 187838
 2013-08-07 00:25:12 +00:00
Akira Hatanaka
1290d365ec [mips] Rename register classes CPURegs and CPU64Regs. 
llvm-svn: 187832
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
4c91ec2ed9 [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of 
instructions defined in MipsInstrInfo.td as codegen-only instructions.

llvm-svn: 187828
 2013-08-06 23:01:10 +00:00
Akira Hatanaka
0eff6770f2 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' 
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.

llvm-svn: 187824
 2013-08-06 22:35:29 +00:00
Akira Hatanaka
354394e047 [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
 2013-08-06 22:20:40 +00:00
NAKAMURA Takumi
0eb9242c56 Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen. 
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

llvm-svn: 187780
 2013-08-06 06:38:37 +00:00
Reed Kotler
d5b7892552 Add the saving of S2. This is needed for some of the floating point 
helper functions. This can be optimized out later when the remaining
parts of the helper function work is moved into the Mips16HardFloat pass.
For now it forces us to use the 32 bit save/restore instructions instead
of the 16 bit ones.

llvm-svn: 187712
 2013-08-04 23:56:53 +00:00
Reed Kotler
338c130a3e Clean up code for Mips16 large frame handling. 
llvm-svn: 187701
 2013-08-04 01:13:25 +00:00
Benjamin Kramer
dad4c5c276 Stop leaking register infos in the disassemblers. 
llvm-svn: 187695
 2013-08-03 22:16:16 +00:00
Akira Hatanaka
9ecf735bdd [mips] Expand vector truncating stores and extending loads. 
llvm-svn: 187667
 2013-08-02 19:23:33 +00:00
Akira Hatanaka
d5137f9c46 [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also, 
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.

llvm-svn: 187632
 2013-08-01 23:14:16 +00:00
Reed Kotler
e5ac0862d0 Fix some issues with Mips16 floating when certain intrinsics are present. 
This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the 
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.

llvm-svn: 187613
 2013-08-01 21:17:53 +00:00
Vladimir Medic
03a431cc4d Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested. 
llvm-svn: 187569
 2013-08-01 09:25:27 +00:00
Reed Kotler
9ef1a8ca7e Fix some misc. issues with Mips16 fp stubs. 
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute

llvm-svn: 187555
 2013-08-01 02:26:31 +00:00
Reed Kotler
7017e6a466 Add an omitted IsCall=1. 
llvm-svn: 187553
 2013-08-01 00:59:06 +00:00
Akira Hatanaka
5651fa36f7 [mips] Rename instruction DANDi to ANDi64. 
No functionality change.

llvm-svn: 187469
 2013-07-31 00:57:41 +00:00
Akira Hatanaka
d0c19bc118 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.

llvm-svn: 187468
 2013-07-31 00:55:34 +00:00
Akira Hatanaka
9f04532f39 [mips] Delete instruction format for "bal". 
llvm-svn: 187443
 2013-07-30 20:42:19 +00:00
Akira Hatanaka
00e403d37b [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that 
turns "bal" into "bgezal".

llvm-svn: 187440
 2013-07-30 20:24:24 +00:00
Vladimir Medic
aafcb477fd This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. 
llvm-svn: 187410
 2013-07-30 10:12:14 +00:00
Akira Hatanaka
591151f071 [mips] Add comment and simplify function. 
llvm-svn: 187371
 2013-07-29 19:08:34 +00:00
Akira Hatanaka
329763d851 [mips] Implement llvm.trap intrinsic. 
Patch by Sasa Stankovic.

llvm-svn: 187244
 2013-07-26 20:58:55 +00:00
Akira Hatanaka
689acaf88f [mips] Fix FP conditional move instructions to have explicit FP condition code 
register operands.

llvm-svn: 187242
 2013-07-26 20:51:20 +00:00
Akira Hatanaka
35c6208a5a [mips] Fix FP branch instructions to have explicit FP condition code register 
operands.

llvm-svn: 187238
 2013-07-26 20:13:47 +00:00
Akira Hatanaka
6e2705a339 [mips] Increase the number of floating point condition code registers to eight. 
llvm-svn: 187234
 2013-07-26 19:03:48 +00:00
Akira Hatanaka
e6ef926882 [mips] Fix floating point branch, comparison, and conditional move instructions 
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233
 2013-07-26 19:01:56 +00:00
Akira Hatanaka
f96ca1bdd3 [mips] Delete register print method MipsInstPrinter::printCPURegs that is not 
needed. The generic method printOperand will do.

No functionality change.

llvm-svn: 187231
 2013-07-26 18:50:42 +00:00
Akira Hatanaka
66dcf905b6 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo 
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229
 2013-07-26 18:34:25 +00:00
Akira Hatanaka
6132f6bc57 [mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFail 
when there wasn't a match. This behavior is consistent with other register
parsing methods.

llvm-svn: 187063
 2013-07-24 18:43:52 +00:00
Petar Jovanovic
22aad9fa66 [test commit] Minor comment change. 
Testing commit access credentials.

llvm-svn: 187032
 2013-07-24 13:02:35 +00:00
Craig Topper
9bf1d910c8 Split generated asm mnemonic matching table into a separate table for each asm variant. 
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.

llvm-svn: 187026
 2013-07-24 07:33:14 +00:00
Akira Hatanaka
39a746e93f [mips] Fix MipsAsmParser::parseCCRRegs. 
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861
 2013-07-22 19:30:38 +00:00
Akira Hatanaka
9f2c66ce7c [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete 
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
 2013-07-22 18:52:22 +00:00
Akira Hatanaka
e50f645c46 [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR. 
No functionality change.

llvm-svn: 186642
 2013-07-19 01:19:52 +00:00