Richard Osborne
400fb5329e
Add instruction encodings / disassembler support for 2rus instructions.
...
llvm-svn: 172985
2013-01-20 17:22:43 +00:00
Richard Osborne
3a5e1fcceb
Add instruction encodings / disassembly support 3r instructions.
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It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
llvm-svn: 172984
2013-01-20 17:18:47 +00:00
Richard Osborne
efed5dbcc7
Add instruction encodings / disassembly support for l2r instructions.
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llvm-svn: 170345
2012-12-17 16:28:02 +00:00
Richard Osborne
b4aaa991f6
Add instruction encodings for PEEK and ENDIN.
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Previously these were marked with the wrong format.
llvm-svn: 170334
2012-12-17 14:23:54 +00:00
Richard Osborne
c66ab02537
Add instruction encodings / disassembly support for rus instructions.
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llvm-svn: 170330
2012-12-17 13:50:04 +00:00
Richard Osborne
92f0d25122
Add instruction encodings for ZEXT and SEXT.
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Previously these were marked with the wrong format.
llvm-svn: 170327
2012-12-17 13:20:37 +00:00
Richard Osborne
cccafe2726
Add instruction encodings / disassembly support for 2r instructions.
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llvm-svn: 170323
2012-12-17 12:29:31 +00:00
Richard Osborne
815fca9724
Add instruction encodings / disassembly support for 0r instructions.
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llvm-svn: 170322
2012-12-17 12:26:29 +00:00
Richard Osborne
91f0d743ac
Add tests for disassembly of 1r XCore instructions.
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llvm-svn: 170295
2012-12-16 18:06:30 +00:00
