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34 Commits

Author SHA1 Message Date
Alp Toker
03b6e12fae Reduce verbiage of lit.local.cfg files 
We can just split targets_to_build in one place and make it immutable.

llvm-svn: 210496
 2014-06-09 22:42:55 +00:00
Daniel Dunbar
a496d61c01 [tests] Cleanup initialization of test suffixes. 
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

llvm-svn: 188513
 2013-08-16 00:37:11 +00:00
Richard Osborne
816f899c45 [XCore] Add LDAPB instructions. 
With the change the disassembler now supports the XCore ISA in its
entirety.

llvm-svn: 181155
 2013-05-05 13:36:53 +00:00
Richard Osborne
6600501755 [XCore] Add BLRB instructions. 
llvm-svn: 181152
 2013-05-05 13:24:16 +00:00
Nico Rieck
3863b37eaf Use object file specific section type for initial text section 
llvm-svn: 179494
 2013-04-14 21:18:36 +00:00
Richard Osborne
25a2bd3084 [XCore] Add bru instruction. 
llvm-svn: 178783
 2013-04-04 20:05:35 +00:00
Richard Osborne
2eabe25672 [XCore] The RRegs register class is a superset of GRRegs. 
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

llvm-svn: 178782
 2013-04-04 19:57:46 +00:00
Richard Osborne
8c4177b262 [XCore] Check disassembly of the st8 instruction. 
llvm-svn: 178689
 2013-04-03 20:07:11 +00:00
Richard Osborne
a7413cf3e7 [XCore] Update disassembler test to improve coverage of the instructions. 
Previously some instructions were unintentionally covered twice and
others were not covered at all.

llvm-svn: 178688
 2013-04-03 20:07:06 +00:00
Richard Osborne
8c3b2c82f6 [XCore] Add missing 2r instructions. 
These instructions are not targeted by the compiler but it is needed for
the MC layer.

llvm-svn: 175407
 2013-02-17 22:38:05 +00:00
Richard Osborne
d7ae1fa57c [XCore] Add TSETR instruction. 
This instruction is not targeted by the compiler but it is needed for the
MC layer.

llvm-svn: 175406
 2013-02-17 22:32:41 +00:00
Richard Osborne
a5892fb541 [XCore] Add missing u10 / lu10 instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175404
 2013-02-17 20:44:48 +00:00
Richard Osborne
8ddb9b973b [XCore] Add missing u6 / lu6 instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175403
 2013-02-17 20:43:17 +00:00
Richard Osborne
373bdcfeb5 [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
 2013-01-27 22:28:30 +00:00
Richard Osborne
72f31f9da6 [XCore] Add missing l2r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173629
 2013-01-27 21:26:02 +00:00
Richard Osborne
70183ce54a [XCore] Add missing 1r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173624
 2013-01-27 20:46:21 +00:00
Richard Osborne
be996a5261 [XCore] Add missing 0r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173623
 2013-01-27 20:42:57 +00:00
Richard Osborne
32d4ba5aeb Add instruction encodings / disassembly support for l4r instructions. 
llvm-svn: 173501
 2013-01-25 21:55:32 +00:00
Richard Osborne
4269c34e3d Add instruction encodings / disassembly support for l5r instructions. 
llvm-svn: 173479
 2013-01-25 20:20:07 +00:00
Richard Osborne
8f90349114 Add instruction encodings / disassembly support for l6r instructions. 
llvm-svn: 173288
 2013-01-23 20:08:11 +00:00
Richard Osborne
6453bd631a Add instruction encodings / disassembly support for u10 / lu10 instructions. 
llvm-svn: 173204
 2013-01-22 22:55:04 +00:00
Richard Osborne
02e7d3f377 Add instruction encodings / disassembly support for u6 / lu6 instructions. 
llvm-svn: 173086
 2013-01-21 20:44:17 +00:00
Richard Osborne
0b3c4f3112 Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
llvm-svn: 173085
 2013-01-21 20:42:16 +00:00
Richard Osborne
c048ec5160 Add instruction encodings / disassembly support for l2rus instructions. 
llvm-svn: 172987
 2013-01-20 18:51:15 +00:00
Richard Osborne
5688672b0b Add instruction encodings / disassembly support for l3r instructions. 
llvm-svn: 172986
 2013-01-20 18:37:49 +00:00
Richard Osborne
400fb5329e Add instruction encodings / disassembler support for 2rus instructions. 
llvm-svn: 172985
 2013-01-20 17:22:43 +00:00
Richard Osborne
3a5e1fcceb Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
 2013-01-20 17:18:47 +00:00
Richard Osborne
efed5dbcc7 Add instruction encodings / disassembly support for l2r instructions. 
llvm-svn: 170345
 2012-12-17 16:28:02 +00:00
Richard Osborne
b4aaa991f6 Add instruction encodings for PEEK and ENDIN. 
Previously these were marked with the wrong format.

llvm-svn: 170334
 2012-12-17 14:23:54 +00:00
Richard Osborne
c66ab02537 Add instruction encodings / disassembly support for rus instructions. 
llvm-svn: 170330
 2012-12-17 13:50:04 +00:00
Richard Osborne
92f0d25122 Add instruction encodings for ZEXT and SEXT. 
Previously these were marked with the wrong format.

llvm-svn: 170327
 2012-12-17 13:20:37 +00:00
Richard Osborne
cccafe2726 Add instruction encodings / disassembly support for 2r instructions. 
llvm-svn: 170323
 2012-12-17 12:29:31 +00:00
Richard Osborne
815fca9724 Add instruction encodings / disassembly support for 0r instructions. 
llvm-svn: 170322
 2012-12-17 12:26:29 +00:00
Richard Osborne
91f0d743ac Add tests for disassembly of 1r XCore instructions. 
llvm-svn: 170295
 2012-12-16 18:06:30 +00:00