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Commit Graph

116 Commits

Author SHA1 Message Date
Andrew Trick
65c09c6381 Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

llvm-svn: 191391
2013-09-25 18:14:12 +00:00
Andrew Trick
768a74cb96 Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

llvm-svn: 184034
2013-06-15 04:50:06 +00:00
Andrew Trick
5d13fe97ed Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032
2013-06-15 04:49:57 +00:00
Arnold Schwaighofer
07e27c55de SubtargetEmitter fix
Don't output data if we are supposed to ignore the record.

Reapply of 183255, I don't think this was causing the tablegen segfault on linux
testers.

llvm-svn: 183311
2013-06-05 14:06:50 +00:00
Arnold Schwaighofer
59cf81c2e1 Revert series of sched model patches until I figure out what is going on.
llvm-svn: 183273
2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
10d37229fb SubtargetEmitter fix
Don't output data if we are supposed to ignore the record.

llvm-svn: 183255
2013-06-04 22:15:41 +00:00
Andrew Trick
17591a1080 Machine model: Generate table entries for super-resources.
Super-resources and resource groups are two ways of expressing
overlapping sets of processor resources. Now we generate table entries
the same way for both so the scheduler never needs to explicitly check
for super-resources.

llvm-svn: 180162
2013-04-23 23:45:16 +00:00
Andrew Trick
69561e2961 Machine model: rewrite a tablegen loop to avoid comparing record pointers.
llvm-svn: 180160
2013-04-23 23:45:11 +00:00
Andrew Trick
19f83ecc6b TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target.

llvm-svn: 178074
2013-03-26 21:36:39 +00:00
Andrew Trick
d9ea1ed5c1 Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

llvm-svn: 177226
2013-03-16 18:58:55 +00:00
Andrew Trick
aab9978611 Fix r177112: Add ProcResGroup.
This is the other half of r177122 that I meant to commit at the same time.

llvm-svn: 177123
2013-03-14 22:47:01 +00:00
Andrew Trick
d133b52150 MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

llvm-svn: 177112
2013-03-14 21:21:50 +00:00
Andrew Trick
ab2046b460 MIsched machine model: tablegen subtarget emitter improvement.
Fix the way resources are counted. I'm taking some time to cleanup the
way MachineScheduler handles in-order machine resources. Eventually
we'll need more PPC/Atom test cases in tree.

llvm-svn: 176390
2013-03-01 23:31:26 +00:00
Andrew Trick
c15e94c204 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

llvm-svn: 171946
2013-01-09 03:36:49 +00:00
Chandler Carruth
3e8b3f66be Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
2012-12-04 10:37:14 +00:00
Rafael Espindola
d404d4c18c Fix a build problem with xlc. The error message was
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+".
"../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate.

Patch by Kai.

llvm-svn: 167311
2012-11-02 20:57:36 +00:00
Joerg Sonnenberger
839f6c1a88 Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 

llvm-svn: 166712
2012-10-25 20:33:17 +00:00
Andrew Trick
13b4f59560 misched: Generate IsBuffered flag for machine resources.
llvm-svn: 165602
2012-10-10 05:43:04 +00:00
Andrew Trick
00263532fa TableGen subtarget emitter, nearly first class support for SchedAlias.
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

llvm-svn: 165179
2012-10-03 23:06:28 +00:00
Andrew Trick
35fd7cbe58 Cleanup TableGen subtarget emitter.
llvm-svn: 165178
2012-10-03 23:06:25 +00:00
Andrew Trick
7a73f9d7f4 Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

llvm-svn: 164451
2012-09-22 02:24:21 +00:00
Andrew Trick
3ed8eed2ed SchedMachineModel: compress the CPU's WriteLatencyTable.
llvm-svn: 164199
2012-09-19 04:43:19 +00:00
Andrew Trick
6cba50cbb4 Replaced ReInitMCSubtargetInfo with InitMCProcessor.
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

llvm-svn: 164105
2012-09-18 05:33:15 +00:00
Andrew Trick
b7b658d440 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
llvm-svn: 164095
2012-09-18 03:41:43 +00:00
Andrew Trick
c2ee4420fd TableGen subtarget emitter. Remove unnecessary header dependence.
llvm-svn: 164094
2012-09-18 03:32:57 +00:00
Andrew Trick
65c7aae93f TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
llvm-svn: 164092
2012-09-18 03:18:56 +00:00
Andrew Trick
2b04a12c0c Backout the wrong subtarget emitter fix
llvm-svn: 164078
2012-09-17 23:14:15 +00:00
Andrew Trick
1956ad7efe Fix release build after reverting
llvm-svn: 164075
2012-09-17 23:05:04 +00:00
Andrew Trick
150c97940b Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
2012-09-17 23:00:42 +00:00
Andrew Trick
9400ee3c79 InitMCProcessor
llvm-svn: 164066
2012-09-17 22:19:12 +00:00
Andrew Trick
7403ff5282 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
llvm-svn: 164062
2012-09-17 22:18:58 +00:00
Andrew Trick
8a499d1f62 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
llvm-svn: 164061
2012-09-17 22:18:55 +00:00
Andrew Trick
f5182127b1 TableGen subtarget emitter. Format and emit data tables for the new machine model.
llvm-svn: 164060
2012-09-17 22:18:50 +00:00
Andrew Trick
ef09f46517 TableGen subtarget emitter. Generate data tables for the new machine model.
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

llvm-svn: 164059
2012-09-17 22:18:48 +00:00
Andrew Trick
cf41195b6a TableGen subtarget emitter. Emit processor resources for the new machine model.
llvm-svn: 164058
2012-09-17 22:18:45 +00:00
Andrew Trick
b324ff57ad TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
2012-09-15 00:19:57 +00:00
Roman Divacky
865ac925b9 Constify subtarget info properly so that we dont cast away the const in
the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual.

llvm-svn: 163251
2012-09-05 21:43:57 +00:00
Andrew Trick
75af469e99 Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

llvm-svn: 161471
2012-08-08 02:44:16 +00:00
Sylvestre Ledru
bf8acb65ac Fix a typo (the the => the)
llvm-svn: 160621
2012-07-23 08:51:15 +00:00
Andrew Trick
48d244a45f Machine model: allow itineraries to be shared by different processor models.
llvm-svn: 159959
2012-07-09 20:43:03 +00:00
Andrew Trick
b9c8074dcd I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00
Andrew Trick
eb9b704bb8 Tweak spelling.
llvm-svn: 159889
2012-07-07 03:59:48 +00:00
Chandler Carruth
15c6f372bc Fix the C++11 build. I hate narrowing conversions.
llvm-svn: 159543
2012-07-02 18:28:34 +00:00
Andrew Trick
baf8a62800 Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.

llvm-svn: 159541
2012-07-02 18:10:42 +00:00
Andrew Trick
251f64f946 Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now.

llvm-svn: 159411
2012-06-29 07:10:41 +00:00
Andrew Trick
52238a0ce5 Make NumMicroOps a variable in the subtarget's instruction itinerary.
The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.

Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.

llvm-svn: 159406
2012-06-29 03:23:18 +00:00
Hal Finkel
db4f1462bf Revert r158679 - use case is unclear (and it increases the memory footprint).
Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027
2012-06-22 20:27:13 +00:00
Andrew Trick
279bd30bbc Use "NoItineraries" for processors with no itineraries.
This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963
2012-06-22 03:58:51 +00:00
Hal Finkel
56f4d93767 Allow up to 64 functional units per processor itinerary.
This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 158679
2012-06-18 21:08:18 +00:00
Hal Finkel
ad971870cc Add two newlines in ParseSubtargetFeatures's debug output after the CPU is printed.
There is otherwise not a newline between the CPU name and the start of the next
pass's output which makes both difficult to read.

llvm-svn: 158350
2012-06-12 04:21:36 +00:00