7 Commits

Author	SHA1	Message	Date
Preston Gurd	8de39bd4f6	Adds Intel Atom scheduling latencies to X86InstrSystem.td. ... llvm-svn: 156194	2012-05-04 19:26:37 +00:00
Preston Gurd	29e60325bf	This patch continues the work of adding instruction latencies for X86 Atom, ... by providing the latencies for the instructions in X86InstrFPStack.td. llvm-svn: 155996	2012-05-02 16:03:35 +00:00
Preston Gurd	d1ae391210	This patch adds X86 instruction itineraries for non-pseudo opcodes in ... X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. llvm-svn: 153033	2012-03-19 14:10:12 +00:00
Andrew Trick	cf63a3d03a	Intel Atom instruction itineraries for mov sign extension and mov zero extension. ... Patch by Tyler Nowicki! llvm-svn: 151743	2012-02-29 19:44:41 +00:00
Preston Gurd	e0609ed607	This patch adds instruction latencies for the SSE instructions ... to the instruction scheduler for the Intel Atom. llvm-svn: 151590	2012-02-27 23:35:03 +00:00
Jia Liu	b077b6085d	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. ... llvm-svn: 150878	2012-02-18 12:03:15 +00:00
Andrew Trick	d09b64fc25	Instruction scheduling itinerary for Intel Atom. ... Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558	2012-02-01 23:20:51 +00:00