2 Commits

Author	SHA1	Message	Date
David Sherwood	4399d793fa	[SVE] Add checks for no warnings in SVE tests ... There are now quite a few SVE tests in LLVM and Clang that do not emit warnings related to invalid use of EVT::getVectorNumElements() and VectorType::getNumElements(). For these tests I have added additional checks that there are no warnings in order to prevent any future regressions. Differential Revision: https://reviews.llvm.org/D80712	2020-06-18 07:49:48 +01:00
Kerry McLaughlin	5992856e99	[AArch64][SVE] Add addressing mode for contiguous loads & stores ... Summary: This patch adds the register + register addressing mode for SVE contiguous load and store intrinsics (LD1 & ST1) Reviewers: sdesmalen, fpetrogalli, efriedma, rengolin Reviewed By: fpetrogalli Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78509	2020-04-21 12:04:43 +01:00