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Commit Graph

12 Commits

Author SHA1 Message Date
Saleem Abdulrasool
1a40ebc0d6 ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

llvm-svn: 199032
2014-01-12 04:36:01 +00:00
Saleem Abdulrasool
b7a097a617 ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

llvm-svn: 198914
2014-01-10 04:38:31 +00:00
Hao Liu
e24e94d1cb revert the test change
llvm-svn: 169823
2012-12-11 06:25:18 +00:00
Hao Liu
a4b44869a6 A newbie try a test commit
llvm-svn: 169821
2012-12-11 06:22:54 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding.
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson
d2cd33b911 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
Bruno Cardoso Lopes
d285a7f27e Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128689
2011-03-31 23:26:08 +00:00
Daniel Dunbar
5827f55cc7 Remove stray empty test file.
llvm-svn: 128640
2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes
392dbfd384 Revert r128632 again, until I figure out what break the tests
llvm-svn: 128635
2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
3b2f5421ac Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
325e16f668 Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.

llvm-svn: 128597
2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes
cebbf7fe68 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

llvm-svn: 128585
2011-03-30 23:32:32 +00:00