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Commit Graph

48041 Commits

Author SHA1 Message Date
Devang Patel
47d505f9ef Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca.
llvm-svn: 134549
2011-07-06 22:06:11 +00:00
Evan Cheng
5b5fb8c78b Add ARM MC registry routines.
llvm-svn: 134547
2011-07-06 22:02:34 +00:00
Evan Cheng
b0e0a318b7 Rename files for consistency.
llvm-svn: 134546
2011-07-06 22:01:53 +00:00
Jim Grosbach
9863be57e0 Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540
2011-07-06 21:35:46 +00:00
Devang Patel
214fa1739f Simplify. Consolidate dbg.declare handling in AllocaPromoter.
llvm-svn: 134538
2011-07-06 21:09:55 +00:00
Andrew Trick
f80318e090 indvars -disable-iv-rewrite: ExprToMap lives in Pass data, so be more
careful about referencing values.

llvm-svn: 134537
2011-07-06 21:07:10 +00:00
Jim Grosbach
99ece4392a Remove un-used encoding info from Pseudo MLAv5.
Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533
2011-07-06 20:57:35 +00:00
Eli Friedman
c3200e013c Fix missing triple support for RTEMS target.
llvm-svn: 134532
2011-07-06 20:56:26 +00:00
Andrew Trick
641b6e4222 indvars -disable-iv-rewrite: Added SimplifyCongruentIVs.
llvm-svn: 134530
2011-07-06 20:50:43 +00:00
Bill Wendling
479007f9af Constify getCompactUnwindRegNum.
llvm-svn: 134527
2011-07-06 20:33:48 +00:00
Evan Cheng
dcd3ea7062 createMCInstPrinter doesn't need TargetMachine anymore.
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
Tobias Grosser
eda1c1a7ce LICM: Remove trailing white spaces
llvm-svn: 134521
2011-07-06 19:20:02 +00:00
Tobias Grosser
97b1ec50e3 LICM: Do not loose alignment on promotion
The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

llvm-svn: 134520
2011-07-06 19:19:55 +00:00
Jakub Staszak
28bcc8673e Introduce "expect" intrinsic instructions.
llvm-svn: 134516
2011-07-06 18:22:43 +00:00
Kevin Enderby
59ba10f2ac Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.

llvm-svn: 134501
2011-07-06 17:23:46 +00:00
Evan Cheng
1112260be0 Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.
llvm-svn: 134457
2011-07-06 02:02:33 +00:00
Dan Gohman
7927fe2250 Remove the ObjC ARC passes from the default optimization list, and add
extension points to be used by clang.

llvm-svn: 134444
2011-07-05 22:01:44 +00:00
Devang Patel
bfd474b954 Preserve debug loc.
llvm-svn: 134441
2011-07-05 21:48:22 +00:00
Benjamin Kramer
b054fe79e3 Use memcmp.
llvm-svn: 134439
2011-07-05 20:28:00 +00:00
Rafael Espindola
9fdf25214f Really fix typo :-(
llvm-svn: 134436
2011-07-05 19:17:10 +00:00
Rafael Espindola
1b99dbcf82 Fix typo.
llvm-svn: 134433
2011-07-05 19:13:27 +00:00
Chad Rosier
bd4367f810 By default mkstemp() creates a temporary file with mode 0600, but the mode
used for open is 0666.  Therefore, add the necessary permission bits for
consistency.
rdar://8621462

llvm-svn: 134430
2011-07-05 18:55:31 +00:00
Jakob Stoklund Olesen
57f59c98ed Break infinite loop when the Hopfield network oscillates.
This is impossible in theory, I can prove it. In practice, our near-zero
threshold can cause the network to oscillate between equally good
solutions.

<rdar://problem/9720596>

llvm-svn: 134428
2011-07-05 18:46:42 +00:00
Rafael Espindola
e54f949f37 Compare all 4 bytes of the header.
llvm-svn: 134427
2011-07-05 18:41:47 +00:00
Eli Friedman
9765ae0015 Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
llvm-svn: 134424
2011-07-05 18:21:20 +00:00
Andrew Trick
8823fc0040 indvars -disable-iv-rewrite: avoid multiple IVs in weird cases.
Putting back the helper that I removed on 7/1 to do this right.

llvm-svn: 134423
2011-07-05 18:19:39 +00:00
Jim Grosbach
315fbb6aea ARM estimateStackSize() needs to account for simplified call frames.
If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.

rdar://9715469

llvm-svn: 134415
2011-07-05 16:05:50 +00:00
Jakob Stoklund Olesen
f95a1068bd Fix PR10277.
Remat during spilling triggers dead code elimination. If a phi-def
becomes unused, that may also cause live ranges to split into separate
connected components.

This type of splitting is different from normal live range splitting. In
particular, there may not be a common original interval.

When the split range is its own original, make sure that the new
siblings are also their own originals. The range being split cannot be
used as an original since it doesn't cover the new siblings.

llvm-svn: 134413
2011-07-05 15:38:41 +00:00
Jakob Stoklund Olesen
c380e517fd Tweak comment and debug output.
llvm-svn: 134412
2011-07-05 15:38:37 +00:00
Michael J. Spencer
342a6e8a5f Fix warnings.
llvm-svn: 134408
2011-07-05 14:48:59 +00:00
Benjamin Kramer
2d266249a6 PR10267: Don't combine an equality compare with an AND into an inequality compare when the AND has more than one use.
This can pessimize code, inequalities are generally more expensive.

llvm-svn: 134379
2011-07-04 20:16:36 +00:00
Roman Divacky
08f7d5cf91 Remove accidentaly left node from previous iteration of the patch.
Noticed by Benjamin Kramer!

llvm-svn: 134376
2011-07-04 15:42:45 +00:00
Rafael Espindola
29113212a6 Move early tail duplication earlier.
This fixes the issue noted in PR10251 where early tail dup of bbs with
indirectbr would cause a bb to be duplicated into a loop preheader
and then into its predecessors, creating phi nodes with identical
operands just before register allocation.

This helps with jsinterp.o size (__TEXT goes from 163568 to 126656)
and a bit with performance 1.005x faster on sunspider (jits still enabled).

The result on webkit with the jit disabled is more significant: 1.021x faster.

llvm-svn: 134372
2011-07-04 04:54:22 +00:00
Rafael Espindola
962773db64 Move most of the pre BB code to TailDuplicateAndUpdate. Change the
HasIndirectbr variable to be just that. No functionality change.

llvm-svn: 134371
2011-07-04 01:21:42 +00:00
Rafael Espindola
ce4f4ff705 Reduce indentation and fix the count of how many PHIs we have inserted.
llvm-svn: 134370
2011-07-04 00:13:36 +00:00
Jakob Stoklund Olesen
9950d41b39 Fix PR10244.
A split point inserted in a block with a landing pad successor may be
hoisted above the call to ensure that it dominates all successors. The
code that handles the rest of the basic block must take this into
account.

I am not including a test case, it would be very fragile. PR10244 comes
from building clang with exceptions enabled.

llvm-svn: 134369
2011-07-04 00:05:28 +00:00
Roman Divacky
eae7daa59b Make the i64 and f64 be 64bit ABI aligned in the target description.
This is what both the ABI and clang says.

llvm-svn: 134367
2011-07-03 16:24:07 +00:00
Rafael Espindola
f04e6b50ca Fix an easy fixme.
llvm-svn: 134364
2011-07-03 05:26:42 +00:00
Duncan Sands
da72617832 Remove unused array.
llvm-svn: 134323
2011-07-02 16:36:24 +00:00
Duncan Sands
3eb91b3dfd Revert previous commit. It seems that whether casting to void
is valid or not depends on which system you build.

llvm-svn: 134321
2011-07-02 13:14:22 +00:00
Duncan Sands
938be63a66 Supress gcc-4.5 warning about the result not being used.
llvm-svn: 134319
2011-07-02 13:06:23 +00:00
Rafael Espindola
cf67208057 Use getVNInfoAt.
llvm-svn: 134312
2011-07-02 07:50:27 +00:00
Jakob Stoklund Olesen
4d72701c7e Consistent diagnostic capitalization and redundant context elimination.
llvm-svn: 134311
2011-07-02 07:23:40 +00:00
Jakob Stoklund Olesen
b94d989634 Better diagnostics when inline asm fails to allocate.
asm.c:2:7: error: ran out of registers during register allocation
  asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9));
        ^

llvm-svn: 134310
2011-07-02 07:17:37 +00:00
Rafael Espindola
a8c92aa8ef Check the VN of the src register at the two copies, not just the
register number.

llvm-svn: 134309
2011-07-02 05:34:02 +00:00
Jakob Stoklund Olesen
c19c47697f Include a source location when complaining about bad inline assembly.
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

llvm-svn: 134307
2011-07-02 03:53:34 +00:00
Andrew Trick
ac38d56661 indvars -disable-iv-rewrite: bug fix involving weird geps and related cleanup.
llvm-svn: 134306
2011-07-02 02:34:25 +00:00
Jakob Stoklund Olesen
60871c3ee0 Use a new strategy for preventing eviction loops in RAGreedy.
Every live range is assigned a cascade number the first time it is
involved in an eviction. As the evictor, it gets a new cascade number.
Every evictee is assigned the same cascade number as the evictor.

Eviction is prohibited if the evictor has a lower assigned cascade
number than the evictee.

This means that assigned cascade numbers are monotonically increasing
with every eviction, yet they are bounded by NextCascade which can only
be incremented by new live ranges. Thus, infinite loops cannot happen,
but eviction cascades can still be triggered by new live ranges as we
want.

Thanks to Andy for explaining this to me.

llvm-svn: 134303
2011-07-02 01:37:09 +00:00
Evan Cheng
09210c224a Add getFeatureBits to extract feature bits for a given CPU.
llvm-svn: 134298
2011-07-02 00:43:44 +00:00
Cameron Zwarich
6ea6623f23 Take a stab at fixing the llvm-x86_64-linux-checks failure.
llvm-svn: 134287
2011-07-01 23:45:21 +00:00