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6 Commits

Author SHA1 Message Date
Daniel Sanders
d13fea547a [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders
a52c7f09dc [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics) 
llvm-svn: 190509
 2013-09-11 10:38:58 +00:00
Daniel Sanders
534d28aa11 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics 
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
 2013-09-11 09:59:17 +00:00
Daniel Sanders
32227b7995 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b) 
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
 2013-09-10 09:51:43 +00:00
Daniel Sanders
6d33546b4a [mips][msa] Summarize tests 
Adds a comment to the start of each test summarizing the area the test covers.

llvm-svn: 189465
 2013-08-28 10:02:29 +00:00
Jack Carter
80890657b3 [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) 
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders

llvm-svn: 188457
 2013-08-15 12:24:57 +00:00