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85 Commits

Author SHA1 Message Date
Chris Lattner
25421b6954 indicate what the native integer types for the target are. 
Please verify.

llvm-svn: 86397
 2009-11-07 19:07:32 +00:00
Evan Cheng
0db11ae5a2 X86 needs critical path anti-dependency breaking. 
llvm-svn: 84931
 2009-10-23 05:57:35 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Evan Cheng
eb82c3743a Turn on post-alloc scheduling for x86. 
llvm-svn: 84431
 2009-10-18 19:57:27 +00:00
Evan Cheng
1f32fa84b0 Oops. I forgot to change the tests first. Disable post-alloc scheduling. 
llvm-svn: 84425
 2009-10-18 18:31:31 +00:00
Evan Cheng
e921ebe70d -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424
 2009-10-18 18:16:27 +00:00
Evan Cheng
e1fbdc5244 Change createPostRAScheduler so it can be turned off at llc -O1. 
llvm-svn: 84273
 2009-10-16 21:06:15 +00:00
Evan Cheng
0a57c7d459 Remove X86Subtarget::IsLinux. It's no longer being used. 
llvm-svn: 84200
 2009-10-15 20:23:21 +00:00
Chris Lattner
e6bd7b39eb rearrange X86ATTAsmPrinter::doFinalization, making a scan of 
the global variable list only happen for COFF targets.

llvm-svn: 82010
 2009-09-16 05:20:33 +00:00
Daniel Dunbar
80f8fc8a2a Make these functions static and local. 
llvm-svn: 80892
 2009-09-03 05:47:34 +00:00
Evan Cheng
6d2d69faf9 X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget. 
No functionality changes.

llvm-svn: 80880
 2009-09-03 04:37:05 +00:00
Chris Lattner
c66a43e2b0 Add support for modeling whether or not the processor has support for 
conditional moves as a subtarget feature.  This is the easy part of 
PR4841.

llvm-svn: 80763
 2009-09-02 05:53:04 +00:00
Chris Lattner
c2a229453e change the -x86-asm-syntax=intel/att flag to be in X86TAI 
instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.

llvm-svn: 78746
 2009-08-11 23:01:09 +00:00
Daniel Dunbar
0b82c938fe Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
 2009-08-02 22:11:08 +00:00
Chris Lattner
478fc8442b remove the now-dead TM argument to these methods. 
llvm-svn: 75276
 2009-07-10 21:00:45 +00:00
Chris Lattner
9c13214ee8 make PIC vs DynamicNoPIC be explicit in PICStyles. 
llvm-svn: 75275
 2009-07-10 20:58:47 +00:00
Chris Lattner
9deef50410 add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode. 
llvm-svn: 75273
 2009-07-10 20:47:30 +00:00
Chris Lattner
6097f82e18 simplify fast isel by using ClassifyGlobalReference. This 
elimiantes the last use of GVRequiresExtraLoad, so delete it.

llvm-svn: 75244
 2009-07-10 07:48:51 +00:00
Chris Lattner
7c038a2b3c eliminate GVRequiresRegister, replacing it with predicates we 
need for other purposes.

llvm-svn: 75243
 2009-07-10 07:38:24 +00:00
Chris Lattner
0cae8c7845 move some classification logic around. Now GVRequiresExtraLoad 
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.

llvm-svn: 75237
 2009-07-10 07:20:05 +00:00
Chris Lattner
41fccd30b7 GVRequiresExtraLoad is now never used for calls, simplify it based on this. 
llvm-svn: 75232
 2009-07-10 05:52:02 +00:00
Chris Lattner
832a724072 actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code 
more complex and slow than just directly testing what we care about.

llvm-svn: 75231
 2009-07-10 05:48:03 +00:00
Chris Lattner
2161376696 There is only one case where GVRequiresExtraLoad returns true for calls: 
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.

llvm-svn: 75230
 2009-07-10 05:45:15 +00:00
Chris Lattner
2e5e403f53 the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it. 
llvm-svn: 75229
 2009-07-10 05:37:11 +00:00
Chris Lattner
cd52f7f20e When in -static mode, force the PIC style to none. Doing this requires fixing 
code which conflated RIPRel PIC with x86-64.  Fix these to just check for X86-64
directly.

llvm-svn: 75092
 2009-07-09 03:15:51 +00:00
David Greene
6be6604b5d Fix a subtarget feature bug. 
llvm-svn: 74428
 2009-06-29 16:51:01 +00:00
David Greene
d33e8e7d83 Add feature flags for AVX and FMA and fix some SSE4A feature flag 
initialization problems.

llvm-svn: 74350
 2009-06-26 22:46:54 +00:00
Chris Lattner
5ef06d833d cosmetic changes. 
llvm-svn: 73836
 2009-06-21 01:27:55 +00:00
Stefanus Du Toit
031dcf315f Update CPU capabilities for AMD machines 
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

llvm-svn: 72434
 2009-05-26 21:04:35 +00:00
Anton Korobeynikov
34fc85e2ee Propagate CPU string out of SubtargetFeatures 
llvm-svn: 72335
 2009-05-23 19:50:50 +00:00
Evan Cheng
e17c02e328 Try again. Allow call to immediate address for ELF or when in static relocation mode. 
llvm-svn: 72160
 2009-05-20 04:53:57 +00:00
Dan Gohman
8271066844 Tidy up #includes, deleting a bunch of unnecessary #includes. 
llvm-svn: 61715
 2009-01-05 17:59:02 +00:00
Evan Cheng
c52f942d67 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. 
llvm-svn: 61557
 2009-01-02 05:35:45 +00:00
Dan Gohman
c3e24d559b Add initial support for back-scheduling address computations, 
especially in the case of addresses computed from loop induction
variables.

llvm-svn: 61075
 2008-12-16 03:35:01 +00:00
Dale Johannesen
c6404f98b2 Forgot a file. 
llvm-svn: 60609
 2008-12-05 21:55:35 +00:00
Duncan Sands
7fd4ea5847 Fix build with gcc-4.4: it doesn't like PICStyle 
being both a namespace and a variable name.

llvm-svn: 60208
 2008-11-28 09:29:37 +00:00
Bill Wendling
618d422cdd Just don't transform this memset into "bzero" if no-builtin is specified. 
llvm-svn: 56888
 2008-09-30 22:05:33 +00:00
Bill Wendling
9ad453e943 Add the new `-no-builtin' flag. This flag is meant to mimic the GCC 
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.

llvm-svn: 56885
 2008-09-30 21:22:07 +00:00
Dan Gohman
8ee7bf053e Use a dedicated IsLinux flag instead of an ELFLinux TargetType. 
llvm-svn: 50649
 2008-05-05 16:11:31 +00:00
Dan Gohman
c860d9c77c Add AsmPrinter support for emitting a directive to declare that 
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634
 2008-05-05 00:28:39 +00:00
Evan Cheng
0585b4bc2a Re-enable SSE4. 
llvm-svn: 49158
 2008-04-03 08:53:29 +00:00
Evan Cheng
f112eb3b1c Temporarily disabling SSE4 until we fix the encoding issues. 
llvm-svn: 49129
 2008-04-03 04:49:54 +00:00
Dan Gohman
168b2b1300 Speculatively micro-optimize memory-zeroing calls on Darwin 10. 
llvm-svn: 49048
 2008-04-01 20:38:36 +00:00
Anton Korobeynikov
dad919f561 Add convenient helper for win64 check. Simplify things slightly. 
llvm-svn: 48691
 2008-03-22 20:57:27 +00:00
Evan Cheng
c3875c88a7 Update comment. 
llvm-svn: 47002
 2008-02-12 07:59:55 +00:00
Evan Cheng
a377b2bbd1 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. 
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax

llvm-svn: 46850
 2008-02-07 08:53:49 +00:00
Nate Begeman
ead8dfeef2 SSE 4.1 Intrinsics and detection 
llvm-svn: 46681
 2008-02-03 07:18:54 +00:00
Chris Lattner
4a0d9c7836 darwin9 and above support aligned common symbols. 
llvm-svn: 45494
 2008-01-02 19:44:55 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Rafael Espindola
fae98471a9 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00