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66 Commits

Author SHA1 Message Date
Elena Demikhovsky
6f951ffaa0 AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions, 
they give better sequences than VPERMI

llvm-svn: 199893
 2014-01-23 14:27:26 +00:00
Elena Demikhovsky
4e0fae8031 AVX-512: optimized scalar compare patterns 
removed AVX512SI format, since it is similar to AVX512BI.

llvm-svn: 199217
 2014-01-14 15:10:08 +00:00
Craig Topper
1c1ecbff81 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
 2014-01-14 07:41:20 +00:00
Elena Demikhovsky
e635ade802 AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.

llvm-svn: 199102
 2014-01-13 12:55:03 +00:00
Elena Demikhovsky
1ecccf9364 AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq. 
llvm-svn: 198745
 2014-01-08 10:54:22 +00:00
Elena Demikhovsky
591c25725f AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without) 
llvm-svn: 198593
 2014-01-06 08:45:54 +00:00
Elena Demikhovsky
935f81172d AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD; 
Optimized a truncate pattern.

llvm-svn: 198562
 2014-01-05 14:21:07 +00:00
Elena Demikhovsky
034a667c24 AVX-512: Added more intrinsics for convert and min/max. 
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557
 2014-01-05 10:46:09 +00:00
Craig Topper
eea372cfa3 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
llvm-svn: 198545
 2014-01-05 04:55:55 +00:00
Craig Topper
4a48c26e38 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Craig Topper
57b949fa83 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Elena Demikhovsky
7174584583 AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Elena Demikhovsky
ee5004d112 AVX-512: Result type of scalar SETCC is MVT::i1 for AVX-512. 
llvm-svn: 198008
 2013-12-25 10:06:40 +00:00
Elena Demikhovsky
2d23dc9650 AVX-512: fixed some patterns for MVT::i1 
llvm-svn: 197981
 2013-12-24 14:24:07 +00:00
Elena Demikhovsky
39275c48ca AVX512: SETCC returns i1 for AVX-512 and i8 for all others 
llvm-svn: 197876
 2013-12-22 10:13:18 +00:00
Elena Demikhovsky
241694a7bc AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey Bader). 
Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.

llvm-svn: 197482
 2013-12-17 08:33:15 +00:00
Elena Demikhovsky
b43ccbc3f7 AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
154413adc2 AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC. 
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).

llvm-svn: 197041
 2013-12-11 14:31:04 +00:00
Elena Demikhovsky
57057960b0 AVX-512: changed intrinsics for mask operations 
llvm-svn: 196918
 2013-12-10 13:53:10 +00:00
Elena Demikhovsky
b3a0e7bbed AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin form 
llvm-svn: 196914
 2013-12-10 11:58:35 +00:00
Cameron McInally
ca9f2bc25b Update AVX512 vector blend intrinsic names. 
llvm-svn: 196581
 2013-12-06 13:35:35 +00:00
Cameron McInally
675f9245aa Add AVX512 patterns for v16i32 broadcast and v2i64 zero extend load. 
Patch by Aleksey Bader.

llvm-svn: 196435
 2013-12-05 00:11:25 +00:00
Cameron McInally
97a9fa294d Fix assembly syntax for AVX512 vector blend instructions. 
llvm-svn: 196393
 2013-12-04 18:05:36 +00:00
Elena Demikhovsky
bac904c06d AVX-512: Handled extractelement from mask vector; 
Added VMOSHDUP/VMOVSLDUP shuffle instructions.

llvm-svn: 194691
 2013-11-14 11:29:27 +00:00
Cameron McInally
02e4f56c18 Add support for AVX512 masked vector blend intrinsics. 
llvm-svn: 194006
 2013-11-04 19:14:56 +00:00
Elena Demikhovsky
841cd7d09e AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Cameron McInally
c38779faad Add AVX512 unmasked integer broadcast intrinsics and support. 
llvm-svn: 193748
 2013-10-31 13:56:31 +00:00
Elena Demikhovsky
0e6849495e AVX-512: PMIN/PMAX intrinsics and patterns 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193497
 2013-10-27 08:18:37 +00:00
Quentin Colombet
5d88e45af6 [X86][AVX512] Add patterns that match the AVX512 floating point register vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193422
 2013-10-25 18:04:12 +00:00
Quentin Colombet
5650890143 [X86][AVX512] Add patterns that match the AVX512 floating point vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193421
 2013-10-25 17:47:18 +00:00
Elena Demikhovsky
da06b9b278 AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsics 
llvm-svn: 193312
 2013-10-24 07:16:35 +00:00
Elena Demikhovsky
3136868b1d AVX-512: aligned / unaligned load and store for 512-bit integer vectors. 
llvm-svn: 193156
 2013-10-22 09:19:28 +00:00
Lang Hames
df2443e32e X86 vector element shift-by-immediate instructions take i8 immediates. Make 
the instruction defenitions and ISEL reflect this.

Prior to this patch these instructions took an i32i8imm, and the high bits were
dropped during encoding. This led to incorrect behavior for shifts by
immediates higher than 255. This patch fixes that issue by detecting large
immediate shifts and returning constant zero (for logical shifts) or capping
the shift amount at an encodable value (for arithmetic shifts).

Fixes <rdar://problem/14968098>

llvm-svn: 193096
 2013-10-21 17:51:24 +00:00
Craig Topper
47d75426b9 Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Elena Demikhovsky
f24ecf7862 AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. 
llvm-svn: 192283
 2013-10-09 08:16:14 +00:00
Andrew Trick
6456fd444d Add missing HasAVX512 predicate. 
This was only working because AVX had cheaper rules in all cases.
I'm sure there are other places in this file where predicates are missing.

llvm-svn: 192276
 2013-10-09 05:11:10 +00:00
Craig Topper
ae27a7b281 Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v' 
llvm-svn: 192272
 2013-10-09 04:24:38 +00:00
Elena Demikhovsky
cb8eaca2e4 AVX-512: added scalar convert instructions and intrinsics. 
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
 2013-10-06 13:11:09 +00:00
Elena Demikhovsky
0ff833ab99 AVX-512: fixed shuffle lowering 
in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055
 2013-10-06 06:11:18 +00:00
Elena Demikhovsky
05028f4106 AVX-512: Fixed encoding of VMOVQ instruction. 
llvm-svn: 191889
 2013-10-03 12:03:26 +00:00
Elena Demikhovsky
ee11e148e9 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target 
llvm-svn: 191818
 2013-10-02 12:20:42 +00:00
Elena Demikhovsky
d336ecd5ad AVX-512: Added TB prefix to all instructions without prefixes, 
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.

llvm-svn: 191812
 2013-10-02 06:39:07 +00:00
Elena Demikhovsky
84c6cd222d AVX-512: Added X86vzmovl patterns 
llvm-svn: 191733
 2013-10-01 08:38:02 +00:00
Craig Topper
60de5044cf Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. 
llvm-svn: 191490
 2013-09-27 07:20:47 +00:00
Elena Demikhovsky
28417de9de AVX-512: Converted to Unix style 
llvm-svn: 190851
 2013-09-17 07:34:34 +00:00
Preston Gurd
0411803c14 Adds support for Atom Silvermont (SLM) - -march=slm 
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.

Auto detects SLM.

Turns on post RA scheduler when generating code for SLM.

llvm-svn: 190717
 2013-09-13 19:23:28 +00:00
Elena Demikhovsky
139f25ed2c AVX-512: implemented extractelement with variable index. 
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.

llvm-svn: 190595
 2013-09-12 08:55:00 +00:00
Elena Demikhovsky
04a636836e AVX-512: Added GATHER and SCATTER instructions. 
llvm-svn: 189729
 2013-09-01 14:24:41 +00:00
Elena Demikhovsky
f05835d923 AVX-512: added extend and truncate instructions. 
llvm-svn: 189580
 2013-08-29 11:56:53 +00:00
Elena Demikhovsky
2f3377ea54 AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS 
llvm-svn: 189472
 2013-08-28 11:21:58 +00:00