Chris Lattner
cd5eeef9ee
Give all operands names
...
llvm-svn: 23357
2005-09-14 21:11:13 +00:00
Chris Lattner
5194ff37c4
Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.
...
I'm not convinced this is all of them, but I can't do much testing, because
IA64 LLC crashes on big programs :(
llvm-svn: 22892
2005-08-19 00:47:42 +00:00
Duraid Madina
b9062e56cf
add the popcount instruction and support this in the isel
...
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...
llvm-svn: 21860
2005-05-11 05:16:09 +00:00
Duraid Madina
0c40c548c0
print negative 64 bit immediates as negative numbers, makes things a little
...
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything
llvm-svn: 21300
2005-04-14 10:08:01 +00:00
Duraid Madina
b9d2d9ac63
* add the shladd instruction
...
* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
llvm-svn: 21282
2005-04-13 06:12:04 +00:00
Chris Lattner
37712352c0
Make sure to realize that calls use their argument regs
...
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
Duraid Madina
d2ae9221c7
assorted fixes:
...
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
llvm-svn: 21221
2005-04-11 05:55:56 +00:00
Duraid Madina
e7412561bf
fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
...
fix hack in division (clean up frcpa instruction)
llvm-svn: 21153
2005-04-08 10:01:48 +00:00
Duraid Madina
5c4a7b68b3
add immediate forms of add, sub, shift
...
llvm-svn: 21129
2005-04-07 12:32:24 +00:00
Duraid Madina
1d156293cb
add fms instruction
...
llvm-svn: 21112
2005-04-06 09:54:09 +00:00
Duraid Madina
d896a18d33
add implicit use op
...
llvm-svn: 21074
2005-04-04 04:50:57 +00:00
Duraid Madina
81675e4031
add fnegabs op
...
llvm-svn: 21022
2005-04-02 10:06:27 +00:00
Duraid Madina
333132da85
add support FNEG and FABS
...
llvm-svn: 21012
2005-04-02 05:18:38 +00:00
Duraid Madina
11ff0a2a5f
add what we need to fudge a 'floating point conditional move', this is
...
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)
llvm-svn: 20954
2005-03-31 07:32:32 +00:00
Duraid Madina
79022e1b87
and so it begins...
...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!
llvm-svn: 20652
2005-03-17 18:17:03 +00:00
