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Author SHA1 Message Date
Reid Spencer
5b747af8e1 These changes are necessary to support the new llvm-config tool. llvm-config 
is a handy tool for users of LLVM who want to be able to quickly get
information about LLVM's configuration. It is intended to be used in the
command line of other tools. Documentation will be forthcoming in a
subsequent patch.

llvm-svn: 26952
 2006-03-22 15:59:55 +00:00
Evan Cheng
f6dc0a7f5e - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
 2006-03-22 08:01:21 +00:00
Chris Lattner
64be951e06 add a note 
llvm-svn: 26950
 2006-03-22 07:33:46 +00:00
Evan Cheng
25440d19b1 Fix PSHUF* and SHUF* jit code emission problems 
llvm-svn: 26949
 2006-03-22 07:10:28 +00:00
Chris Lattner
ab22cd5c33 Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. 
Now you can build a tool with just the JIT or just the interpreter.

llvm-svn: 26946
 2006-03-22 06:07:50 +00:00
Chris Lattner
05c3c52edf wrap lines to 80 columns. 
Add static JITCtor/InterpCtor fields

llvm-svn: 26945
 2006-03-22 06:06:37 +00:00
Chris Lattner
5141ebb2c4 This has been implemented. Tweak it into another note 
llvm-svn: 26944
 2006-03-22 05:33:23 +00:00
Chris Lattner
f84f3bf95b When possible, custom lower 32-bit SINT_TO_FP to this: 
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943
 2006-03-22 05:30:33 +00:00
Chris Lattner
cfbce5186a Add support for "ri" addressing modes where the immediate is a 14-bit field 
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.

llvm-svn: 26942
 2006-03-22 05:26:03 +00:00
Chris Lattner
1554bf155e fix a warning 
llvm-svn: 26941
 2006-03-22 04:18:34 +00:00
Evan Cheng
7aac4350c7 Some splat and shuffle support. 
llvm-svn: 26940
 2006-03-22 02:53:00 +00:00
Evan Cheng
b6c46ed8c9 Add a couple more pseudo instructions. 
llvm-svn: 26939
 2006-03-22 02:52:03 +00:00
Chris Lattner
c8696247e5 Endianness does not affect the order of vector fields. This fixes 
SingleSource/UnitTests/Vector/build.c

llvm-svn: 26936
 2006-03-22 01:46:54 +00:00
Chris Lattner
2e606dc60f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp 
llvm-svn: 26935
 2006-03-22 01:44:36 +00:00
Chris Lattner
51b4436cce Enclose some variables in a scope to avoid error with some gcc versions 
llvm-svn: 26934
 2006-03-22 00:12:37 +00:00
Evan Cheng
7c8d7bc4b3 Didn't mean to check this in. No MMX support yet. 
llvm-svn: 26933
 2006-03-21 23:04:23 +00:00
Evan Cheng
47dd756c72 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
 2006-03-21 23:01:21 +00:00
Chris Lattner
12e4b95b6b add expand support for extractelement 
llvm-svn: 26931
 2006-03-21 21:02:03 +00:00
Chris Lattner
31a93c7740 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
llvm-svn: 26930
 2006-03-21 20:51:05 +00:00
Evan Cheng
d21f479c5f Don't forget to promote xform function to an explicit node for def : Pat<> 
patterns.

llvm-svn: 26929
 2006-03-21 20:44:17 +00:00
Chris Lattner
b90d9241c1 add some trivial support for extractelement. 
llvm-svn: 26928
 2006-03-21 20:44:12 +00:00
Chris Lattner
9f8cfe5ab4 add some nodes for extractelement 
llvm-svn: 26927
 2006-03-21 20:43:08 +00:00
Chris Lattner
140be98ab8 Don't emit pseudo instructions! 
llvm-svn: 26926
 2006-03-21 20:19:37 +00:00
Chris Lattner
128089ae91 Add a hacky workaround for crashes due to vectors live across blocks. 
Note that this code won't work for vectors that aren't legal on the
target.  Improvements coming.

llvm-svn: 26925
 2006-03-21 19:20:37 +00:00
Nate Begeman
4bd73df4bd Update readme 
llvm-svn: 26924
 2006-03-21 18:58:20 +00:00
Chris Lattner
df3a0c94e2 Add an integer splat test 
llvm-svn: 26923
 2006-03-21 18:27:27 +00:00
Chris Lattner
414fed4108 Print absolute memory references like this: 
lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.

llvm-svn: 26922
 2006-03-21 17:21:13 +00:00
Evan Cheng
a56ed39464 Combine 2 entries 
llvm-svn: 26921
 2006-03-21 07:18:26 +00:00
Evan Cheng
f8d8d45ff8 Add a note about x86 register coallescing 
llvm-svn: 26920
 2006-03-21 07:12:57 +00:00
Evan Cheng
6ec225863c - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919
 2006-03-21 07:09:35 +00:00
Chris Lattner
4da595f4c8 minor code simplification 
llvm-svn: 26918
 2006-03-21 06:42:58 +00:00
Chris Lattner
6417236c41 With Evan's latest tblgen patch, this code is obsolete, thanks Evan! 
llvm-svn: 26917
 2006-03-21 06:37:40 +00:00
Reid Spencer
fcd146d8c2 Cause the various warnings list to be generated via a <ul> list with 
text enclosed in <tt>. This ensures that (a) the text is in a fixed width
font (to indicated generated text) and (b) the text wraps without causing
the page width to be extended. The main result of this is that the report
will wrap to conform to the window size in which it is displayed instead of
having a very wide length if a warning message is long.

llvm-svn: 26916
 2006-03-21 01:21:39 +00:00
Chris Lattner
eaf4338f8d Document ENABLE_ASSERTIONS=1 
llvm-svn: 26915
 2006-03-21 01:10:57 +00:00
Chris Lattner
79d9b6db8a Enable assertions to be enabled in release builds by building with 
make ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1

llvm-svn: 26914
 2006-03-21 01:06:41 +00:00
Chris Lattner
acb2506622 When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. 
llvm-svn: 26913
 2006-03-21 00:51:38 +00:00
Chris Lattner
9e611a25c7 minor note 
llvm-svn: 26912
 2006-03-21 00:47:09 +00:00
Evan Cheng
a4db61ddc1 x86 ISD::SCALAR_TO_VECTOR support. 
llvm-svn: 26911
 2006-03-21 00:33:35 +00:00
Evan Cheng
d90127aafd Junk unused vector register classes. 
llvm-svn: 26910
 2006-03-21 00:30:59 +00:00
Evan Cheng
e87add642d The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't 
one, i.e. don't select it.

llvm-svn: 26909
 2006-03-20 22:53:06 +00:00
Chris Lattner
cdc4657988 Handle constant addresses more efficiently, folding the low bits into the 
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr

llvm-svn: 26908
 2006-03-20 22:38:22 +00:00
Chris Lattner
a498dd25d9 remove dead variable 
llvm-svn: 26907
 2006-03-20 22:37:23 +00:00
Chris Lattner
b59ca7a728 new testcase 
llvm-svn: 26906
 2006-03-20 22:37:05 +00:00
Nate Begeman
31da564faa Move some common data structures between dom and pdom into the base class 
llvm-svn: 26905
 2006-03-20 19:32:48 +00:00
Chris Lattner
978628896b Fix a couple of bugs in permute/splat generate, thanks to Nate for actually 
figuring these out! :)

llvm-svn: 26904
 2006-03-20 18:26:51 +00:00
Evan Cheng
26861ff2af Option -enable-x86-lsr has been removed 
llvm-svn: 26903
 2006-03-20 18:26:11 +00:00
Chris Lattner
5c994b8c63 reenable this hack, the tblgen version isn't quite ready 
llvm-svn: 26902
 2006-03-20 17:54:43 +00:00
Chris Lattner
fb0e160aa5 Fix the pattern for VADDUWM, add i32 splat 
llvm-svn: 26901
 2006-03-20 17:51:58 +00:00
Evan Cheng
57da1afbc8 Use tblgen'd VECTOR_SHUFFLE selection code. 
llvm-svn: 26900
 2006-03-20 08:14:16 +00:00
Evan Cheng
38a1075865 It should be ok for a xform output type to be different from input type. 
llvm-svn: 26899
 2006-03-20 08:09:17 +00:00