Dan Gohman
cd25487258
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
...
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Owen Anderson
604f9f722d
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
...
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
llvm-svn: 53058
2008-07-02 23:41:07 +00:00
Anton Korobeynikov
03a62267fe
Make intel asmprinter child of generic asmprinter, not x86 shared asm printer. This leads to some code duplication, which will be resolved later.
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llvm-svn: 52858
2008-06-28 11:07:54 +00:00
Evan Cheng
2dfe8c2435
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
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llvm-svn: 52308
2008-06-16 07:33:11 +00:00
Dan Gohman
f9d5689496
Change target-specific classes to use more precise static types.
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This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
2008-05-14 01:58:56 +00:00
Bill Wendling
646f3458c4
Constify the machine instruction passed into the
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"is{Trivially,Really}ReMaterializable" methods.
llvm-svn: 51001
2008-05-12 20:54:26 +00:00
Nicolas Geoffray
82baa2d2c6
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
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llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Evan Cheng
38a755499d
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
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llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Dan Gohman
2b96ce84aa
Add explicit keywords.
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llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Christopher Lamb
0f1c32eb63
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
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Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
Christopher Lamb
74f4d837df
Recommitting parts of r48130. These do not appear to cause the observed failures.
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llvm-svn: 48223
2008-03-11 10:09:17 +00:00
Evan Cheng
067ecbc341
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
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llvm-svn: 48167
2008-03-10 19:31:26 +00:00
Christopher Lamb
32e5ce3d96
Allow insert_subreg into implicit, target-specific values.
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Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
Andrew Lenharth
ad29a49169
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
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llvm-svn: 47795
2008-03-01 13:37:02 +00:00
Dan Gohman
cabaec582f
Rename MRegisterInfo to TargetRegisterInfo.
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llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Evan Cheng
90f03a0b88
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
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llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Chris Lattner
bfffa4f21e
Simplify the side effect stuff a bit more and make licm/sinking
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both work right according to the new flags.
This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.
It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.
I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.
llvm-svn: 45843
2008-01-10 23:08:24 +00:00
Chris Lattner
f83aae613c
rename TargetInstrDescriptor -> TargetInstrDesc.
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Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner
55343065e3
remove MachineOpCode typedef.
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llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Owen Anderson
f19692b2f6
Move even more functionality from MRegisterInfo into TargetInstrInfo.
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Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Owen Anderson
2adf8c5533
Move some more functionality from MRegisterInfo to TargetInstrInfo.
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llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Bill Wendling
92d8ff0471
Machine LICM will check that operands are defined outside of the loop. Also
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check that register isn't 0 before going further.
llvm-svn: 45498
2008-01-02 21:10:40 +00:00
Owen Anderson
e6856128ab
Move some more instruction creation methods from RegisterInfo into InstrInfo.
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llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
1285ec2ae7
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
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a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
ae7e2c1e03
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
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Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Bill Wendling
4c22e299ef
If we have a load of a global address that's not modified during the
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function, then go ahead and hoist it out of the loop. This is the result:
$ cat a.c
volatile int G;
int A(int N) {
for (; N > 0; --N)
G++;
}
$ llc -o - -relocation-model=pic
_A:
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LBB1_2: # bb
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %esi
incl (%esi)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
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$ llc -o - -relocation-model=pic -machine-licm
_A:
...
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %eax
LBB1_2: # bb
incl (%eax)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
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I'm limiting this to the MOV32rm x86 instruction for now.
llvm-svn: 45444
2007-12-30 03:18:58 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Bill Wendling
e5af8b6e5c
Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
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based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.
llvm-svn: 45132
2007-12-17 23:07:56 +00:00
Bill Wendling
8d8d9a2f5e
Reverting 44702. It wasn't correct to rename them.
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llvm-svn: 44727
2007-12-08 23:58:46 +00:00
Bill Wendling
d10837def7
Renaming:
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isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable
llvm-svn: 44702
2007-12-08 07:17:56 +00:00
Duncan Sands
26ef2a1767
Move getX86RegNum into X86RegisterInfo and use it
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in the trampoline lowering. Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.
llvm-svn: 41577
2007-08-29 19:01:20 +00:00
Dan Gohman
9cbc3fb1ab
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Dale Johannesen
62f49dd524
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
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llvm-svn: 37578
2007-06-14 22:03:45 +00:00
Dan Gohman
35f2b4d716
Add a target hook to allow loads from constant pools to be rematerialized, and an
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implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
Evan Cheng
90b0ff05f6
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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llvm-svn: 37193
2007-05-18 00:18:17 +00:00
Bill Wendling
3b1189afbf
Add support for our first SSSE3 instruction "pmulhrsw".
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llvm-svn: 35869
2007-04-10 22:10:25 +00:00
Jim Laskey
23ed7d2625
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Evan Cheng
2c35691a02
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
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immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
llvm-svn: 32215
2006-12-05 04:01:03 +00:00
Evan Cheng
bf13611e84
Match TargetInstrInfo changes.
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llvm-svn: 32098
2006-12-01 21:52:58 +00:00
Chris Lattner
dcfee77788
add another target hook for branch folding.
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llvm-svn: 31262
2006-10-28 17:29:57 +00:00
Chris Lattner
016325f336
Implement support for branch condition reversal.
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llvm-svn: 31099
2006-10-21 05:52:40 +00:00
Chris Lattner
62a0f00312
Implement branch analysis/xform hooks required by the branch folding pass.
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llvm-svn: 31065
2006-10-20 17:42:20 +00:00
Chris Lattner
7353b07275
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
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llvm-svn: 31024
2006-10-17 22:41:45 +00:00
Chris Lattner
bea7a9de50
remove some dead code
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llvm-svn: 30938
2006-10-13 20:40:42 +00:00
Evan Cheng
15dd42884e
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00
Evan Cheng
bdb6af8e7d
Fix a build breaker.
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llvm-svn: 28574
2006-05-30 21:45:53 +00:00
Chris Lattner
f604017e47
Patches to make the LLVM sources more -pedantic clean. Patch provided
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by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
Evan Cheng
d49a6d7065
ImmMask should be 3 for a two-bit field; Compact X86II
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llvm-svn: 28381
2006-05-18 06:27:15 +00:00
Chris Lattner
15cb732cd7
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
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llvm-svn: 25913
2006-02-02 20:12:32 +00:00