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Author SHA1 Message Date
Akira Hatanaka
224ebf0e1b Implement N32/64 calling convention. Patch by Liu. 
llvm-svn: 140401
 2011-09-23 19:08:15 +00:00
Akira Hatanaka
8573d26722 Make FGR64RegisterClass available if target is Mips64. 
llvm-svn: 140397
 2011-09-23 18:28:39 +00:00
Akira Hatanaka
1e2b0369c6 Add definitions of 64-bit register files. Add code for returning Mips64's sets of 
callee-saved registers and reserved registers.

llvm-svn: 140395
 2011-09-23 18:11:56 +00:00
Justin Holewinski
b89e54799d PTX: Fix parameter order bug 
llvm-svn: 140394
 2011-09-23 17:59:11 +00:00
Wesley Peck
aa6f35fe05 Fix a couple of 80 column violations. 
patch contributed by Jia Liu!

llvm-svn: 140391
 2011-09-23 17:24:41 +00:00
Justin Holewinski
d0190a31d3 PTX: Cleanup unused code in PTXMachineFunctionInfo 
llvm-svn: 140390
 2011-09-23 17:15:53 +00:00
Justin Holewinski
0ae669e25c PTX: Fix another 80-column violation 
llvm-svn: 140387
 2011-09-23 16:50:35 +00:00
Justin Holewinski
1c0e0dcfbe PTX: Handle function call return values 
llvm-svn: 140386
 2011-09-23 16:48:41 +00:00
Richard Osborne
0ec86a885b Fix 80 column violations. 
Original patch by Liu.

llvm-svn: 140385
 2011-09-23 16:28:10 +00:00
Duncan Sands
6d3fe8d11a Implement Chris's suggestion of legalizing the various SSE and AVX 
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.

llvm-svn: 140383
 2011-09-23 16:10:22 +00:00
Garrison Venn
d0c68eb6c0 Modified demo to use 3.0 resume instruction vs calling _Unwine_Resume. 
Also conducted some reformatting. As the LLVM coding standard doc does not
seem to touch on how to align function arguments, and format code longer than
80 cols in general, the confusion persists. There is the golden rule, but as
this code has gone through several styles to deal with this, the golden rule
seems to be ignored. The latest reformatting effort tries to match the other
source files as much as possible.

Tested on OS X 10.7.1 with, and without the OLD_EXC_SYSTEM defined. Have NOT
tested on LINUX.

llvm-svn: 140379
 2011-09-23 14:45:10 +00:00
Justin Holewinski
0231798704 PTX: Start fixing function calls 
llvm-svn: 140378
 2011-09-23 14:31:12 +00:00
Justin Holewinski
0bb6486c58 PTX: Remove PTX calling convention files 
llvm-svn: 140377
 2011-09-23 14:18:27 +00:00
Justin Holewinski
6d69389691 [PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns 
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
 lib/Target/PTX/PTXInstrInfo.td          |  165 ++++++++++++++++++++----------
 lib/Target/PTX/PTXIntrinsicInstrInfo.td |   88 +++++++++++------
 2 files changed, 167 insertions(+), 86 deletions(-)

llvm-svn: 140376
 2011-09-23 14:18:24 +00:00
Justin Holewinski
6353459757 PTX: Generalize handling of .param types 
llvm-svn: 140375
 2011-09-23 14:18:22 +00:00
Justin Holewinski
72d8a2bd94 PTX: Cleanup unused code in the PTXMFInfoExtract pass 
llvm-svn: 140374
 2011-09-23 14:18:19 +00:00
Duncan Sands
51ea179ef5 Tweak the handling of MERGE_VALUES nodes: remove the need for 
DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).

llvm-svn: 140373
 2011-09-23 13:59:22 +00:00
Nadav Rotem
8f2bc520f5 Vector-Select: Address one of the problems in pr10902. Add handling for the 
integer-promotion of CONCAT_VECTORS.

Test: test/CodeGen/X86/widen_shuffle-1.ll

This patch fixes the above tests (when running in with -promote-elements).

llvm-svn: 140372
 2011-09-23 09:33:24 +00:00
Craig Topper
655f8a01e6 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
llvm-svn: 140370
 2011-09-23 06:57:25 +00:00
Akira Hatanaka
102afe6879 Add definitions of 64-bit int registers. 
llvm-svn: 140366
 2011-09-23 02:33:15 +00:00
Akira Hatanaka
f213002a1c Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363
 2011-09-23 00:58:33 +00:00
Eric Christopher
f79f875df9 We're no longer going to bother supporting platforms that don't 
support C89.

We probably didn't support them anyways.

llvm-svn: 140361
 2011-09-23 00:53:10 +00:00
Eli Friedman
6f0131b3a7 PR10989: Don't print .hidden on Windows. 
llvm-svn: 140356
 2011-09-23 00:13:02 +00:00
Eli Friedman
31c7bde95a PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) 
llvm-svn: 140355
 2011-09-22 23:41:28 +00:00
Akira Hatanaka
c83a0bb4b6 Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354
 2011-09-22 23:31:54 +00:00
Owen Anderson
a8bb97f784 Add new files to CMake. 
llvm-svn: 140352
 2011-09-22 23:20:48 +00:00
Dan Gohman
d63418e497 Fix SimplifySelectCC to add newly created nodes to the DAGCombiner 
worklist, as it may be possible to perform further optimization on them.

llvm-svn: 140349
 2011-09-22 23:01:29 +00:00
Jakob Stoklund Olesen
a608b612f1 Add support for GR32 <-> FR32 cross class copies. 
We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

llvm-svn: 140348
 2011-09-22 22:45:24 +00:00
Benjamin Kramer
a83c5493ec Update CMake build. 
llvm-svn: 140347
 2011-09-22 22:38:34 +00:00
Owen Anderson
d3151e11e8 Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable. 
These are very much a work in progress, and not really useful yet.

llvm-svn: 140345
 2011-09-22 22:32:22 +00:00
Jakob Stoklund Olesen
dedb558e4d Constrain register classes instead of emitting copies. 
Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

llvm-svn: 140340
 2011-09-22 21:39:34 +00:00
Jakob Stoklund Olesen
1d3105c3d3 Add a MinNumRegs argument to MRI::constrainRegClass(). 
The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339
 2011-09-22 21:39:31 +00:00
Duncan Sands
1da590b589 Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332
 2011-09-22 20:15:48 +00:00
Eli Friedman
6e15091fc6 PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl. 
llvm-svn: 140327
 2011-09-22 18:56:30 +00:00
Chris Lattner
966f637ca8 Resynch intro to section with copyright section. 
llvm-svn: 140326
 2011-09-22 18:54:31 +00:00
Akira Hatanaka
82aaeed7f4 Print parentheses in next line. 
llvm-svn: 140325
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
7bba6afecf Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
llvm-svn: 140324
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
eaf1e32694 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319
 2011-09-22 17:57:32 +00:00
Bill Wendling
4a26d03528 Use the C personality function instead of the C++ personality function. 
llvm-svn: 140318
 2011-09-22 17:56:40 +00:00
Akira Hatanaka
329b07db41 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.

llvm-svn: 140316
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
96122b7f72 Add F31 to the set of callee-saved registers. 
llvm-svn: 140315
 2011-09-22 17:35:03 +00:00
Galina Kistanova
95b887e917 Fix for warnings: ignoring return value of ‘write’, declared with attribute warn_unused_result. 
llvm-svn: 140314
 2011-09-22 17:33:24 +00:00
Akira Hatanaka
6b99d9b0f3 Fix typo. 
llvm-svn: 140313
 2011-09-22 17:26:58 +00:00
Justin Holewinski
9acce6aa64 PTX: fixup test cases for register changes 
llvm-svn: 140311
 2011-09-22 16:45:51 +00:00
Justin Holewinski
a43c9dc50c PTX: Remove physical register defs 
llvm-svn: 140310
 2011-09-22 16:45:48 +00:00
Justin Holewinski
04f4046d9f PTX: Use .param space for device function return values on SM 2.0+, and attempt 
to fix up parameter passing on SM < 2.0

llvm-svn: 140309
 2011-09-22 16:45:46 +00:00
Justin Holewinski
987b8f7a69 PTX: Fix style issues 
llvm-svn: 140308
 2011-09-22 16:45:43 +00:00
Justin Holewinski
815227205d PTX: Fixup codegen to handle emission of virtual registers. 
llvm-svn: 140307
 2011-09-22 16:45:40 +00:00
Justin Holewinski
1dd4cf37f8 PTX: Customize codegen passes in backend 
llvm-svn: 140306
 2011-09-22 16:45:37 +00:00
Justin Holewinski
fee8e64e4d PTX: Add new PTX-specific register allocator that keeps virtual registers 
instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305
 2011-09-22 16:45:33 +00:00