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Commit Graph

188262 Commits

Author SHA1 Message Date
Alina Sbirlea
21c5787ed7 [MemorySSA] Moving at the end often means before terminator.
Moving accesses in MemorySSA at InsertionPlace::End, when an instruction is
moved into a block, almost always means insert at the end of the block, but
before the block terminator. This matters when the block terminator is a
MemoryAccess itself (an invoke), and the insertion must be done before
the terminator for the update to be correct.

Insert an additional position: InsertionPlace:BeforeTerminator and update
current usages where this applies.

Resolves PR44027.
2019-11-20 17:11:00 -08:00
Craig Topper
aedb09ba63 [X86] Fix i16->f128 sitofp to promote the i16 to i32 before trying to form a libcall.
Previously one of the test cases added here gave an error.
2019-11-20 17:09:32 -08:00
Craig Topper
d77164bb2a [X86] Fix f128->i16 fptosi to promote the i16 to i32 before trying to form a libcall.
Previously one of the test cases added here gave an error.
2019-11-20 17:09:31 -08:00
Adrian Prantl
d2a56513d0 Fix an offset underflow bug in DwarfExpression when describing small values with subregisters
DwarfExpression::addMachineReg() knows how to build a larger register
that isn't expressible in DWARF by combining multiple
subregisters. However, if the entire value fits into just one
subregister, it would still emit the other subregisters, leading to
all sorts of inconsistencies down the line.

This patch fixes that by moving an already existing(!) check whether
the subregister's offset is before the end of the value to the right
place.

rdar://problem/57294211

Differential Revision: https://reviews.llvm.org/D70508
2019-11-20 17:07:54 -08:00
Philip Reames
f12fe720d1 Precommit tests for forthcoming widenable.condition transforms 2019-11-20 17:02:04 -08:00
Josh Kunz
e084a10545 [docs] Tiny rewording in the portability FAQ entry
The entry reads better with these two words swapped.
2019-11-20 16:40:30 -08:00
Alina Sbirlea
27de8339d1 [MemorySSA] Update analysis when the terminator is a memory instruction.
Update MemorySSA when moving the terminator instruction, as that may be a memory touching instruction.
Resolves PR44029.
2019-11-20 16:36:52 -08:00
Reid Kleckner
ce03a2121f [ADT] Move to_vector from STLExtras.h to SmallVector.h
Nothing breaks, so this probably has zero impact, but it seems nice,
since to_vector is more like makeArrayRef, and should really live in
SmallVector.h.
2019-11-20 16:35:19 -08:00
Peter Collingbourne
f0d31eaac6 gn build: check-clang depends on llvm-cxxfilt. 2019-11-20 16:25:54 -08:00
Eric Christopher
3d68f1e222 Revert "[AArch64] Add the pipeline model for Exynos M5"
as it's causing test failures in llvm-mca.

This reverts commit 9bdfee2a3bd13d405ce1592930182f23849d2897.
2019-11-20 16:04:52 -08:00
Eric Christopher
7b534b3c55 Temporarily Revert "[SLP] allow forming 2-way reduction patterns" and update testcases.
After speaking with Sanjay - seeing a number of miscompiles and working
on tracking down a testcase. None of the follow on patches seem to
have helped so far.

This reverts commit 8a0aa5310bccbb42d16d11db090419fcefdd1376.
2019-11-20 16:00:53 -08:00
Eric Christopher
6d982d0bf7 Temporarily Revert "Temporarily Revert "[SLP] allow forming 2-way reduction patterns""
as there were testcase changes after that need to also be reverted.

This reverts commit cd8748a15f2d18861b3548eb26ed2b52e5ee50b4.
2019-11-20 15:39:47 -08:00
Yonghong Song
1efbe554a0 [BPF] Fix a bug in peephole optimization
One of current peephole optimiations is to remove SLL/SRL if
the sub register has been zero extended. This phase has two bugs
and one limitations.

First, for the physical subregister used in pseudo insn COPY
like below, it permits incorrect optimization.
    %0:gpr32 = COPY $w0
    ...
    %4:gpr = MOV_32_64 %0:gpr32
    %5:gpr = SLL_ri %4:gpr(tied-def 0), 32
    %6:gpr = SRA_ri %5:gpr(tied-def 0), 32
The $w0 could be from the return value of a previous function call
and its upper 32-bit value might contain some non-zero values.
The same applies to function arguments.

Second, the current code may permits removing SLL/SRA like below:
    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY %0:gpr32
    ...
    %4:gpr = MOV_32_64 %1:gpr32
    %5:gpr = SLL_ri %4:gpr(tied-def 0), 32
    %6:gpr = SRA_ri %5:gpr(tied-def 0), 32
The reason is that it did not follow def-use chain to skip all
intermediate 32bit-to-32bit COPY instructions.

The current implementation is also very conservative for PHI
instructions. If any PHI insn component is another PHI or COPY insn,
it will just permit SLL/SRA.

This patch fixed the issue as follows:
 - During def/use chain traversal, if any physical register is read,
   SLL/SRA will be preserved as these physical registers are mostly
   from function return values or current function arguments.
 - Recursively visit all COPY and PHI instructions.
2019-11-20 15:19:59 -08:00
Eric Christopher
fd20022682 Temporarily Revert "[SLP] allow forming 2-way reduction patterns"
After speaking with Sanjay - seeing a number of miscompiles and working
on tracking down a testcase. None of the follow on patches seem to
have helped so far.

This reverts commit 7ff57705ba196ce649d6034614b3b9df57e1f84f.
2019-11-20 15:19:31 -08:00
Lang Hames
4783cb036c [Support][Error] Unfriend FileError. It is not special.
FileError doesn't need direct access to Error's internals as it can access the
payload via handleErrors.

(ErrorList remains special: it is not possible to write a handler for it, due
to the special auto-unpacking treatment that it receives from handleErrors.)
2019-11-20 15:08:37 -08:00
Evandro Menezes
4ab9ed6b8f [AArch64] Add the pipeline model for Exynos M5
Add the scheduling and cost models for Exynos M5.
2019-11-20 16:56:07 -06:00
Evgenii Stepanov
60a4b60e92 Cherry-pick gtest fix for asan tests.
Summary:
681454dae4

Clone+exec death test allocates a single page of stack to run chdir + exec on.
This is not enough when gtest is built with ASan and run on particular
hardware.

With ASan on x86_64, ExecDeathTestChildMain has frame size of 1728 bytes.

Call to chdir() in ExecDeathTestChildMain ends up in
_dl_runtime_resolve_xsavec, which attempts to save register state on the stack;
according to cpuid(0xd) XSAVE register save area size is 2568 on my machine.

This results in something like this in all death tests:
  Result: died but not with expected error.
  ...
  [  DEATH   ] AddressSanitizer:DEADLYSIGNAL
  [  DEATH   ] =================================================================
  [  DEATH   ] ==178637==ERROR: AddressSanitizer: stack-overflow on address ...

PiperOrigin-RevId: 278709790

Reviewers: pcc

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70332
2019-11-20 14:12:51 -08:00
Piotr Sobczak
1af506a300 [AMDGPU][SILoadStoreOptimizer] Merge TBUFFER loads/stores
Summary: Extend SILoadStoreOptimizer to merge tbuffer loads and stores.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69794
2019-11-20 22:59:30 +01:00
Krzysztof Parzyszek
e8804e3800 [Hexagon] Fix two testcase errors
This fixes issues discovered in https://reviews.llvm.org/D63973.
2019-11-20 15:06:35 -06:00
Craig Topper
079091fb71 [X86] Mark vector STRICT_FP_ROUND as Legal instead of Custom.
The Custom handler doesn't do anything for these nodes anyway.

SelectionDAGISel won't mutate them if they are Legal or Custom.
X86 has custom code for mutating them due to missing isel patterns.
When the isel patterns are added Legal will be the right answer.
So go ahead a change it now since that's where we'll end up.
2019-11-20 13:03:51 -08:00
Philip Reames
75e10dcf71 Move widenable branch formation into makeGuardControlFlowExplicit helper
This is mostly NFC, but I removed the setting of the guard's calling convention onto the WC call.  Why?  Because it was untested, and was producing an ill defined output as the declaration's convention wasn't been changed leaving a mismatch which is UB.
2019-11-20 12:54:05 -08:00
Stanislav Mekhanoshin
2fa5c427a3 [AMDGPU] Fixed mfma test check. NFC. 2019-11-20 12:33:12 -08:00
Michael Liao
d8d1683ed2 [AMDGPU] Keep consistent check of legal addressing mode.
Summary:
- Add test cases for GFX10, which has narrower offset range compared to
  GFX9.

Reviewers: rampitec, arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70473
2019-11-20 15:08:17 -05:00
Jonas Devlieghere
c1440088ae [FileCollector] Ignore empty paths.
Don't insert empty strings into the StringSet<> because that triggers an
assert in its implementation.
2019-11-20 10:57:44 -08:00
Ulrich Weigand
5c3ed730d8 [SystemZ] Avoid mixing strict and non-strict FP operations in tests
This is to prepare for having the IR verifier reject mixed functions.
Note that fp-strict-mul-02.ll and fp-strict-mul-04.ll still remain
to be fixed.
2019-11-20 19:51:30 +01:00
Craig Topper
37995d5160 [SelectionDAG][X86] Mutate strictFP nodes to non-strict in DoInstructionSelection when the node is marked Expand rather than when it is not Legal.
This allows operations that are marked Custom, but have some type
combinations that are legal to get past this code.

Add custom mutation code to X86's Select function for the nodes
that don't have isel patterns yet.
2019-11-20 10:36:02 -08:00
Ulrich Weigand
f3ab4849fb [SystemZ] Use fneg in test cases
Now that we have fneg, prefer using it over "fsub -0.0, ...".
This helps in particular with strict FP tests, as fneg does
not raise any exceptions.
2019-11-20 19:08:27 +01:00
James Y Knight
30aba84435 Rename 'DenormalMode' in CommandFlags.inc to 'DenormalFPMath', as its
option is actually named anyhow.

This avoids a conflict with the llvm::DenormalMode enum in
FloatingPointMode.h.
2019-11-20 12:16:14 -05:00
Xiangling Liao
496500a08b A fix of the bug introduced by previous lowering in asm patch.
Differential Revision: https://reviews.llvm.org/D70243
2019-11-20 11:29:10 -05:00
Xing Xue
7defe1736c [AIX][XCOFF] Add support for generating assembly code for one-byte mergable strings
This patch adds support for generating assembly code for one-byte mergeable strings.

Generating assembly code for multi-byte mergeable strings and the `XCOFF` object code for mergeable strings will be supported later.

Reviewers: hubert.reinterpretcast, jasonliu, daltenty, sfertile, DiggerLin, Xiangling_L

Reviewed by: daltenty

Subscribers: wuzish, nemanjai, hiraditya, kbarton, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70310
2019-11-20 11:26:49 -05:00
LLVM GN Syncbot
7cb6af25c8 gn build: Merge a03435ec8e2 2019-11-20 15:28:09 +00:00
Xiangling Liao
930ceb8d4e [AIX] Lowering jump table, constant pool and block address in asm
This patch lowering jump table, constant pool and block address in assembly.
1. On AIX, jump table index is always relative;
2. Put CPI and JTI into ReadOnlySection until we support unique data sections;
3. Create the temp symbol for block address symbol;
4. Update MIR testcases and add related assembly part;

Differential Revision: https://reviews.llvm.org/D70243
2019-11-20 10:27:15 -05:00
Pavel Labath
e992eb498a Recommit "[DWARF] Add an api to get "interpreted" location lists"
This recommits 089c0f581492cd6e2a3d2927be3fbf60ea2d7e62, which was
reverted due to failing tests on big endian machines. It includes a fix
which I believe (I don't have BE machine) should fix this issue. The fix
consists of correcting the invocation DWARFYAML::EmitDebugSections,
which was missing one (default) function arguments, and so didn't
actually force the little-endian mode.

The original commit message follows.

Summary:
This patch adds DWARFDie::getLocations, which returns the location
expressions for a given attribute (typically DW_AT_location). It handles
both "inline" locations and references to the external location list
sections (currently only of the DW_FORM_sec_offset type). It is
implemented on top of DWARFUnit::findLoclistFromOffset, which is also
added in this patch. I tried to make their signatures similar to the
equivalent range list functionality.

The actual location list interpretation logic is in
DWARFLocationTable::visitAbsoluteLocationList. This part is not
equivalent to the range list code, but this deviation is motivated by a
desire to reuse the same location list parsing code within lldb.

The functionality is tested via a c++ unit test of the DWARFDie API.

Reviewers: dblaikie, JDevlieghere, SouraVX

Subscribers: mgorny, hiraditya, cmtice, probinson, llvm-commits, aprantl

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70394
2019-11-20 16:24:11 +01:00
Sanjay Patel
ccaf0491bd [SLP] reduce duplicate CHECK lines in tests; NFC 2019-11-20 10:12:54 -05:00
Dmitry Preobrazhensky
465cd6bb4c [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen
These opcodes use indirect register addressing so they need special handling by codegen (currently missing).

Reviewers: vpykhtin, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D70400
2019-11-20 17:57:50 +03:00
Simon Atanasyan
1938f5c5b0 [mips] Define mem_simm# operands using tblgen foreach loop. NFC 2019-11-20 17:42:15 +03:00
David Zarzycki
87c9c2362c [SelectionDAG] Combine U{ADD,SUB}O diamonds into {ADD,SUB}CARRY
Summary:
Convert (uaddo (uaddo x, y), carryIn) into addcarry x, y, carryIn if-and-only-if the carry flags of the first two uaddo are merged via OR or XOR.

Work remaining: match ADD, etc.

Reviewers: craig.topper, RKSimon, spatel, niravd, jonpa, uweigand, deadalnix, nikic, lebedev.ri, dmgreen, chfast

Reviewed By: lebedev.ri

Subscribers: chfast, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70079
2019-11-20 16:25:42 +02:00
LLVM GN Syncbot
52ebfb3921 gn build: Merge 72d2929c52a 2019-11-20 14:15:38 +00:00
Pavel Labath
4a15f473a7 Revert "[DWARF] Add an api to get "interpreted" location lists"
The test fails on big endian machines.

This reverts commit 089c0f581492cd6e2a3d2927be3fbf60ea2d7e62 and the
subsequent attempt to fix in 82dc32e2d456c75d08bc9ffe97def409ee5a03cd.
2019-11-20 15:15:22 +01:00
Anna Welker
a741347da4 [ARM][MVE] Select vqabs
Adds a pattern to ARMInstrMVE.td to use a VQABS
  instruction if an equivalent multi-instruction
  construct is found.

  Differential revision: https://reviews.llvm.org/D70181
2019-11-20 13:58:38 +00:00
Pavel Labath
c5cbb240dd Big-endian fix to DWARFDieTest (089c0f58)
Hardcode the DWARFContext to little-endian. I don't have a BE machine to
test this on, but I believe this should address the ppc64be failure.
2019-11-20 14:35:41 +01:00
Alex Richardson
14c4d851d4 [update_cc_test_checks.py] Add the --function-signature flag
Summary:
This was added to update_test_checks.py in D68819 and I believe having it
in update_cc_test_checks.py is also useful.

Reviewers: jdoerfert, MaskRay

Reviewed By: MaskRay

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70429
2019-11-20 13:23:26 +00:00
Alex Richardson
b8a003f5ca [UptestTestChecks][NFC] Share some common command line options code
Summary:
Add a function common.parse_commandline_args() that adds options common
to all tools (--verbose and --update-only) and returns the parsed
commandline arguments. I plan to use the shared parsing of --verbose in a
follow-up commit to remove most of the `if args.verbose:` checks in the
scripts.

Reviewers: xbolva00, MaskRay

Reviewed By: MaskRay

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70428
2019-11-20 13:23:26 +00:00
Simon Atanasyan
2188b5a3f1 [mips] Put conditions when we need to expand memory operand into a separate function. NFC
`expandMemInst` expects instruction with 3 or 4 operands and the last
operand requires expanding. It's redundant to scan all operands in a
loop. We can check the last operands.
2019-11-20 16:07:16 +03:00
Simon Atanasyan
dfb0b51d81 [mips] Make MipsAsmParser::isEvaluated static function. NFC 2019-11-20 16:07:16 +03:00
Dmitry Preobrazhensky
8dbe434a1d [AMDGPU][DPP] Corrected DPP combiner
Added a check to make sure that the selected dpp opcode is supported by target.

Reviewers: vpykhtin, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D70402
2019-11-20 15:56:45 +03:00
LLVM GN Syncbot
0075942ee9 gn build: Merge 089c0f58149 2019-11-20 12:30:58 +00:00
Clement Courbet
e88e0737f1 [CodeGen][NFC] Regenerate load-combine test with update_llc_test.
To prepare for D27861.
2019-11-20 13:27:31 +01:00
Pavel Labath
97e9d6eacf [DWARF] Add an api to get "interpreted" location lists
Summary:
This patch adds DWARFDie::getLocations, which returns the location
expressions for a given attribute (typically DW_AT_location). It handles
both "inline" locations and references to the external location list
sections (currently only of the DW_FORM_sec_offset type). It is
implemented on top of DWARFUnit::findLoclistFromOffset, which is also
added in this patch. I tried to make their signatures similar to the
equivalent range list functionality.

The actual location list interpretation logic is in
DWARFLocationTable::visitAbsoluteLocationList. This part is not
equivalent to the range list code, but this deviation is motivated by a
desire to reuse the same location list parsing code within lldb.

The functionality is tested via a c++ unit test of the DWARFDie API.

Reviewers: dblaikie, JDevlieghere, SouraVX

Subscribers: mgorny, hiraditya, cmtice, probinson, llvm-commits, aprantl

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70394
2019-11-20 13:25:18 +01:00
Djordje Todorovic
a84a1220f4 [DebugInfo] Remove the DIFlagArgumentNotModified debug info flag
Due to changes in D68206, we remove the DIFlagArgumentNotModified
and its usage.

Differential Revision: https://reviews.llvm.org/D68207
2019-11-20 13:18:40 +01:00