Vikram S. Adve
30cc745aec
BA has only one argument.
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Added LDFSR, LDXFSR, STFSR and STXFSR.
Fixed operands info for RDCCR, WRCCR.
llvm-svn: 2835
2002-07-08 23:25:17 +00:00
Vikram S. Adve
7b84ec22d8
Change latencies for Load, Store and Branch instructions.
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llvm-svn: 1965
2002-03-24 03:33:53 +00:00
Vikram S. Adve
1c7f39af14
Change latency of SETX to improve schedule -- just a hack.
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llvm-svn: 1304
2001-11-14 15:54:44 +00:00
Ruchira Sasanka
0f38515129
Added M_PSEUDO_FLAG for SETX .. instr
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llvm-svn: 1301
2001-11-14 15:35:13 +00:00
Vikram S. Adve
cb87df31db
Fixed instruction information for RDCCR and WRCCR.
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Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).
llvm-svn: 1120
2001-11-04 19:34:49 +00:00
Ruchira Sasanka
20c3c4be28
Added code to support correct saving of %ccr across calls
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llvm-svn: 1111
2001-11-03 19:59:59 +00:00
Vikram S. Adve
64c463355b
Add SETX instruction for 64-bit constants.
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Add M_CC_FLAG for many instructions that use int or fp CC registers.
llvm-svn: 1006
2001-10-28 21:41:01 +00:00
Vikram S. Adve
bebf9c9763
Added SAVE and RESTORE. Duplicated JMPL into JMPLCALL and JMPLRET,
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which have the same opcode and operands but different flags.
llvm-svn: 938
2001-10-22 13:32:55 +00:00
Vikram S. Adve
5201cd7f93
Change latency of setuw and setsw to 2 cycles.
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llvm-svn: 681
2001-09-30 23:46:57 +00:00
Chris Lattner
2635fee3a8
Seperate instruction definitions into new SparcInstr.def file
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Move contents of SparcMachineInstrDesc[] out of SparcInternals.h
into Sparc.cpp
llvm-svn: 644
2001-09-19 15:56:23 +00:00
