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69722 Commits

Author SHA1 Message Date
Reid Kleckner
f2dda46680 Teach the inliner how to preserve musttail invariants
The interesting case is what happens when you inline a musttail call
through a musttail call site.  In this case, we can't break perfect
forwarding or allow any stack growth.

Instead of merging control flow from the inlined return instruction
after a musttail call into the body of the caller, leave the inlined
return instruction in the caller so that the musttail call stays in the
tail position.

More work is required in http://reviews.llvm.org/D3630 to handle the
case where the inlined function has dynamic allocas or byval arguments.

Reviewers: chandlerc

Differential Revision: http://reviews.llvm.org/D3491

llvm-svn: 208910
2014-05-15 20:11:28 +00:00
David Blaikie
d7c6f6cc69 DebugInfo: Add FIXME regarding DILexicalBlock uniquing fields.
llvm-svn: 208909
2014-05-15 20:09:55 +00:00
Simon Atanasyan
c65a88ecce [obj2yaml][ELF] Do not print empty Link and Info fields for ELF sections.
llvm-svn: 208905
2014-05-15 18:04:02 +00:00
Juergen Ributzka
2a4b7a30e4 Revert "[PM] Add pass run listeners to the pass manager."
Revert the current implementation and C API. New implementation and C APIs are
in the works.

llvm-svn: 208904
2014-05-15 17:49:20 +00:00
Bradley Smith
2a2f59ce3b [ARM64] Improve diagnostics for Cn operands in SYS instructions
llvm-svn: 208902
2014-05-15 16:28:32 +00:00
Andrea Di Biagio
ac4cb52129 [X86] Teach the backend how to fold SSE4.1/AVX/AVX2 blend intrinsics.
Added target specific combine rules to fold blend intrinsics according
to the following rules:
 1) fold(blend A, A, Mask) -> A;
 2) fold(blend A, B, <allZeros>) -> A;
 3) fold(blend A, B, <allOnes>) -> B.

Added two new tests to verify that the new folding rules work for all
the optimized blend intrinsics.

llvm-svn: 208895
2014-05-15 15:18:15 +00:00
Zoran Jovanovic
5a4694735d [mips][mips64r6] Add CLASS.fmt instructions
Differential Revision: http://reviews.llvm.org/D3712

llvm-svn: 208894
2014-05-15 15:16:36 +00:00
Zoran Jovanovic
f64b55bdcb [mips][mips64r6] Add RINT.fmt instructions
Differential Revision: http://reviews.llvm.org/D3711

llvm-svn: 208892
2014-05-15 15:04:37 +00:00
Zoran Jovanovic
6de41d285d [mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructions
Differential Revision: http://reviews.llvm.org/D3710

llvm-svn: 208891
2014-05-15 14:58:42 +00:00
Zoran Jovanovic
bc63e943e1 [mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions
Differential Revision: http://reviews.llvm.org/D3709

llvm-svn: 208890
2014-05-15 14:54:06 +00:00
Tom Stellard
dbf9b9b7af R600/SI: Stop using VSrc_* as the default register class for types.
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

llvm-svn: 208888
2014-05-15 14:41:57 +00:00
Tom Stellard
d01bb8adfa R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
This prevents a future commit from regressing the load-i1.ll test.

llvm-svn: 208887
2014-05-15 14:41:55 +00:00
Tom Stellard
77051e93a5 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
llvm-svn: 208886
2014-05-15 14:41:54 +00:00
Tom Stellard
efb8470c62 R600/SI: Use VALU instructions for i1 ops
llvm-svn: 208885
2014-05-15 14:41:50 +00:00
Tim Northover
ac5dac4c75 TableGen: use correct MIOperand when printing aliases
Previously, TableGen assumed that every aliased operand consumed precisely 1
MachineInstr slot (this was reasonable because until a couple of days ago,
nothing more complicated was eligible for printing).

This allows a couple more ARM64 aliases to print so we can remove the special
code.

On the X86 side, I've gone for explicit AT&T size specifiers as the default, so
turned off a few of the aliases that would have just started printing.

llvm-svn: 208880
2014-05-15 13:36:01 +00:00
Daniel Sanders
f89f1dcf37 [mips][mips64r6] Add bitswap, and dbitswap
Summary: Depends on D3728

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3729

llvm-svn: 208877
2014-05-15 12:18:23 +00:00
Jay Foad
2827803889 Instead of littering asserts throughout the code after every call to
computeKnownBits, consolidate them into one assert at the end of
computeKnownBits itself.

llvm-svn: 208876
2014-05-15 12:12:55 +00:00
Tim Northover
ed117bb644 ARM64: print correct aliases for NEON mov & mvn instructions
In all cases, if a "mov" alias exists, it is the canonical form of the
instruction. Now that TableGen can support aliases containing syntax variants,
we can enable them and improve the quality of the asm output.

llvm-svn: 208874
2014-05-15 12:11:02 +00:00
Daniel Sanders
883f9833f0 [mips][mips64r6] Add align and dalign
Summary: Depends on D3689

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3728

llvm-svn: 208872
2014-05-15 12:06:36 +00:00
Tim Northover
4ba95d4483 TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

llvm-svn: 208867
2014-05-15 11:16:32 +00:00
Tim Northover
83bd592b77 ARM64: add correct vector registers during asm parsing
Previously, we ignored the difference between V64 and V128 when parsing
assembly: they both got mapped to registers in the FPR128 class. This is
basically harmless at the moment because they both print and encode the same
way. However, it will affect the printing of aliases.

llvm-svn: 208866
2014-05-15 11:16:19 +00:00
Bradley Smith
8301057544 [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses
llvm-svn: 208864
2014-05-15 11:08:30 +00:00
Bradley Smith
c77dfa4453 [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted
llvm-svn: 208863
2014-05-15 11:07:57 +00:00
Bradley Smith
ffae33a2db [ARM64] Add/Fixup diagnostics for floating point immediates
llvm-svn: 208862
2014-05-15 11:07:28 +00:00
Bradley Smith
5033c221c9 [ARM64] Add condition code operand type such that proper diagnostics can be emitted
llvm-svn: 208861
2014-05-15 11:06:51 +00:00
Bradley Smith
b8ba322e07 [ARM64] Add more simple diagnostics for immediate/shift ranges
llvm-svn: 208860
2014-05-15 11:06:16 +00:00
Daniel Sanders
17f37b6f3f [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

llvm-svn: 208858
2014-05-15 10:45:58 +00:00
Daniel Sanders
f29be03643 [mips][mips64r6] Add aui, daui, dahi, and dati
Summary: Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3759

llvm-svn: 208857
2014-05-15 10:27:19 +00:00
Chandler Carruth
0d35e1f8fc Teach the constant folder to look through bitcast constant expressions
much more effectively when trying to constant fold a load of a constant.
Previously, we only handled bitcasts by trying to find a totally generic
byte representation of the constant and use that. Now, we look through
the bitcast to see what constant we might fold the load into, and then
try to form a constant expression cast of the found value that would be
equivalent to loading the value.

You might wonder why on earth this actually matters. Well, turns out
that the Itanium ABI causes us to create a single array for a vtable
where the first elements are virtual base offsets, followed by the
virtual function pointers. Because the array is homogenous the element
type is consistently i8* and we inttoptr the virtual base offsets into
the initial elements.

Then constructors bitcast these pointers to i64 pointers prior to
loading them. Boom, no more constant folding of virtual base offsets.
This is the first fix to LLVM to address the *insane* performance Eric
Niebler discovered with Clang on his range comprehensions[1]. There is
more to come though, this doesn't *really* fix the problem fully.

[1]: http://ericniebler.com/2014/04/27/range-comprehensions/

llvm-svn: 208856
2014-05-15 09:56:28 +00:00
Daniel Sanders
ca9cbc1b8b [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.
Summary:
They aren't implemented for any ISA at the moment.

Depends on D3670

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3671

llvm-svn: 208855
2014-05-15 09:47:43 +00:00
Dinesh Dwivedi
2381ae3d5b Reverting r208848, reason: build failure: sanitizer-x86_64-linux-bootstrap/builds/3399
llvm-svn: 208852
2014-05-15 08:22:55 +00:00
Dinesh Dwivedi
74c9400378 Added instcombine for 'MIN(MIN(A, 27), 93)' and 'MAX(MAX(A, 93), 27)'
MIN(MIN(A, 23), 97) -> MIN(A, 23)
MAX(MAX(A, 97), 23) -> MAX(A, 97)

Differential Revision: http://reviews.llvm.org/D3629

llvm-svn: 208849
2014-05-15 06:13:40 +00:00
Dinesh Dwivedi
de41090110 Added inst combine transforms for single bit tests from Chris's note
if ((x & C) == 0) x |= C becomes x |= C
if ((x & C) != 0) x ^= C becomes x &= ~C
if ((x & C) == 0) x ^= C becomes x |= C
if ((x & C) != 0) x &= ~C becomes x &= ~C
if ((x & C) == 0) x &= ~C becomes nothing

Z3 Verifications code for above transform
http://rise4fun.com/Z3/Pmsh

Differential Revision: http://reviews.llvm.org/D3717

llvm-svn: 208848
2014-05-15 06:01:33 +00:00
Jonathan Roelofs
9a09decd36 Fix some dyslexia in an assert message
llvm-svn: 208842
2014-05-15 02:24:50 +00:00
Alp Toker
18115693f7 Fix typos
llvm-svn: 208839
2014-05-15 01:52:21 +00:00
Jiangning Liu
ecd097d587 [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.
llvm-svn: 208837
2014-05-15 01:33:17 +00:00
Eric Christopher
f26f61b12b Move the TargetMachine MC options to MCTargetOptions. No functional
change.

llvm-svn: 208832
2014-05-15 01:08:00 +00:00
David Majnemer
809b8a331d InstCombine: Optimize -x s< cst
Summary:
This gets rid of a sub instruction by moving the negation to the
constant when valid.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3773

llvm-svn: 208827
2014-05-15 00:02:20 +00:00
David Blaikie
071f1f0679 DwarfDebug: Don't set frame index locations on abstract variables.
Abstract variables should never have/use locations. In this case the
data wasn't used, so no functional change intended here, just
simplification.

llvm-svn: 208820
2014-05-14 22:51:59 +00:00
David Blaikie
ef32c3bf98 DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.
Many old tests using prior schemas still had some brokenness here (both
indirect arrays and arrays with single bogus elements). Fixed those up
so they don't hit the new assertions.

Also reduced nesting in some places, etc.

llvm-svn: 208817
2014-05-14 21:52:46 +00:00
David Blaikie
03965d6089 DebugInfo: Assert that a CU's subprogram list contains only subprograms.
llvm-svn: 208816
2014-05-14 21:52:37 +00:00
Kevin Enderby
7558c9cb9b Teach llvm-nm to know about fat archives (aka MachOUniversal files
containing archives).  First step as other tools will be updated next.

llvm-svn: 208812
2014-05-14 21:18:50 +00:00
Jay Foad
e0eac700cb Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
2014-05-14 21:14:37 +00:00
David Majnemer
6098432810 InstSimplify: Optimize signed icmp of -(zext V)
Summary:
We know that -(zext V) will always be <= zero, simplify signed icmps
that have these.

Uncovered using http://www.cs.utah.edu/~regehr/souper/

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3754

llvm-svn: 208809
2014-05-14 20:16:28 +00:00
David Blaikie
4e2a4915ae DebugInfo: Do not delay attaching DW_AT_inline attribute to abstract definitions.
This is just unneccessary - we only create abstract definitions when
we're inlining anyway, so there's no reason to delay this to see if
we're going to inline anything.

llvm-svn: 208798
2014-05-14 17:58:53 +00:00
Christian Pirker
7dd3a40e09 ARM-BE: test files for vector argument passing
Reviewed at http://reviews.llvm.org/D3766

llvm-svn: 208793
2014-05-14 16:59:44 +00:00
Christian Pirker
f835f2f7be [ARM64-BE] Fix byte order of CIE and FDE frames for exception handling
Reviewed at http://reviews.llvm.org/D3741

llvm-svn: 208792
2014-05-14 16:51:58 +00:00
Logan Chien
fb407ff21d Fix ARM EHABI when function has landingpad and nounwind.
If the function has the landingpad instruction, then the
handlerdata should be emitted even if the function has
nouwnind attribute.  Otherwise, following code will not
work:

    void test1() noexcept {
      try {
        throw_exception();
      } catch (...) {
        log_unexpected_exception();
      }
    }

Since the cantunwind was incorrectly emitted and the
LSDA is not available.

llvm-svn: 208791
2014-05-14 16:38:30 +00:00
Benjamin Kramer
56a86f3d17 X86: If we have an instruction that sets a flag and a zero test on the input of that instruction try to eliminate the test.
For example
	tzcntl	%edi, %ebx
	testl %edi, %edi
	je	.label

can be rewritten into
	tzcntl	%edi, %ebx
	jb 	.label

A minor complication is that tzcnt sets CF instead of ZF when the input
is zero, we have to rewrite users of the flags from ZF to CF. Currently
we recognize patterns using lzcnt, tzcnt and popcnt.

Differential Revision: http://reviews.llvm.org/D3454

llvm-svn: 208788
2014-05-14 16:14:45 +00:00
Daniel Sanders
2b18784a55 [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3670

llvm-svn: 208784
2014-05-14 15:29:44 +00:00