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17470 Commits

Author SHA1 Message Date
Johnny Chen
b3130a03a7 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
 2011-04-06 18:27:46 +00:00
Rafael Espindola
2d898c22cd Add another case we are not optimizing. 
llvm-svn: 129012
 2011-04-06 17:35:32 +00:00
Rafael Espindola
115cbc12ea The original issue has been fixed by not doing unnecessary sign extensions. 
Change the test to force a sign extension and expose the problem again.

llvm-svn: 129011
 2011-04-06 17:19:35 +00:00
Johnny Chen
765dec3867 Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
 2011-04-06 01:18:32 +00:00
Owen Anderson
b59504a1a1 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 
llvm-svn: 128965
 2011-04-05 23:55:28 +00:00
Johnny Chen
48b39632aa Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
 2011-04-05 23:28:00 +00:00
Bob Wilson
89dce9ab06 Clean up some code for clarity. 
llvm-svn: 128953
 2011-04-05 23:03:25 +00:00
Owen Anderson
c8ceb7246f Revert r128946 while I figure out why it broke the buildbots. 
llvm-svn: 128951
 2011-04-05 23:03:06 +00:00
Johnny Chen
359b9a2331 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
 2011-04-05 22:57:07 +00:00
Owen Anderson
809f1a74d1 Give RSBS and RSCS the pseudo treatment. 
llvm-svn: 128946
 2011-04-05 22:42:54 +00:00
Johnny Chen
cf11408b65 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
 2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
 2011-04-05 21:49:44 +00:00
Owen Anderson
b73d1741c6 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. 
llvm-svn: 128940
 2011-04-05 21:48:57 +00:00
Johnny Chen
b50ab34083 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
 2011-04-05 20:32:23 +00:00
Johnny Chen
4a15bdc1aa ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
llvm-svn: 128913
 2011-04-05 19:42:11 +00:00
Jim Grosbach
7bdaed671d Make second source operand of LDRD pre/post explicit. 
Finish what r128736 started.

llvm-svn: 128903
 2011-04-05 18:40:13 +00:00
Johnny Chen
d37098ae32 Constants with multiple encodings (ARM): 
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

llvm-svn: 128897
 2011-04-05 18:02:46 +00:00
Johnny Chen
626c0a35f6 Check for invalid register encodings for UMAAL and friends where: 
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

llvm-svn: 128895
 2011-04-05 17:43:10 +00:00
Owen Anderson
b314020ff7 Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value. 
llvm-svn: 128892
 2011-04-05 17:24:25 +00:00
Bill Wendling
a8db395dc1 Revamp the SjLj "dispatch setup" intrinsic. 
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>

llvm-svn: 128873
 2011-04-05 01:37:43 +00:00
Eric Christopher
b04934036a Just use BL all the time. It's safer that way. 
Fixes rdar://9184526

llvm-svn: 128869
 2011-04-05 00:39:26 +00:00
Johnny Chen
785ab1531b Fix SRS/SRSW encoding bits. 
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.

llvm-svn: 128864
 2011-04-05 00:16:18 +00:00
Johnny Chen
92c33bafac A8.6.105 MUL 
Inst{15-12} should be specified as 0b0000.

rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL

llvm-svn: 128862
 2011-04-04 23:57:05 +00:00
Johnny Chen
eb8e7684b9 RFE encoding should also specify the "should be" encoding bits. 
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.

llvm-svn: 128859
 2011-04-04 23:39:08 +00:00
Joerg Sonnenberger
4033708a54 Make OpcodeMask an unsigned long long literal to deal with overflow. 
llvm-svn: 128847
 2011-04-04 21:38:17 +00:00
Johnny Chen
7fb247299a Fix incorrect alignment for NEON VST2b32_UPD. 
rdar://problem/9225433

llvm-svn: 128841
 2011-04-04 20:35:31 +00:00
Jakob Stoklund Olesen
c4092e120d Insert code in the right location when lowering PowerPC atomics. 
This causes defs to dominate uses, no instructions after terminators, and other
goodness.

llvm-svn: 128836
 2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes
74363376e4 - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

llvm-svn: 128832
 2011-04-04 17:18:19 +00:00
Akira Hatanaka
54ae678397 Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. 
llvm-svn: 128830
 2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen
8eef3feba8 PowerPC atomic pseudos clobber CR0, they don't read it. 
llvm-svn: 128829
 2011-04-04 17:07:09 +00:00
Jakob Stoklund Olesen
de8d7a7432 Use X0 instead of R0 for the zero register on ppc64. 
The 32-bit R0 cannot be used where a 64-bit register is expected.

llvm-svn: 128828
 2011-04-04 17:07:06 +00:00
Joerg Sonnenberger
1cbd300346 Add support for the VIA PadLock instructions. 
llvm-svn: 128826
 2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
2bfb3e48e7 Expand Op0Mask by one bit in preparation for the PadLock prefixes. 
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.

llvm-svn: 128822
 2011-04-04 15:58:30 +00:00
Jay Foad
fc232f270b Remove some support for ReturnInsts with multiple operands, and for 
returning a scalar value in a function whose return type is a single-
element structure or array.

llvm-svn: 128810
 2011-04-04 07:44:02 +00:00
Che-Liang Chiou
c4a22b7cd5 ptx: support setp's 4-operand format 
llvm-svn: 128767
 2011-04-02 08:51:39 +00:00
Cameron Zwarich
9573b6277e Do some peephole optimizations to remove pointless VMOVs from Neon to integer 
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

llvm-svn: 128759
 2011-04-02 02:40:43 +00:00
Johnny Chen
dcd29e054c Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289

llvm-svn: 128757
 2011-04-02 02:24:54 +00:00
Akira Hatanaka
9a001f303e Undo changes mistakenly made in revision 128750. 
llvm-svn: 128751
 2011-04-02 00:26:12 +00:00
Akira Hatanaka
6b700f35aa Insert space before ';' to prevent warnings. 
llvm-svn: 128750
 2011-04-02 00:15:58 +00:00
Johnny Chen
6f10cfdf01 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276

llvm-svn: 128749
 2011-04-01 23:30:25 +00:00
Johnny Chen
b308662930 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120

llvm-svn: 128748
 2011-04-01 23:15:50 +00:00
Johnny Chen
845caa871c Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

llvm-svn: 128746
 2011-04-01 22:32:51 +00:00
Evan Cheng
4531994839 Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009 
llvm-svn: 128743
 2011-04-01 22:09:28 +00:00
Akira Hatanaka
9f4b4d2dc1 Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed. 
llvm-svn: 128742
 2011-04-01 21:56:02 +00:00
Akira Hatanaka
9257b524eb Simplifies logic for printing target flags. 
llvm-svn: 128741
 2011-04-01 21:41:06 +00:00
Owen Anderson
48048d179c When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately. 
llvm-svn: 128739
 2011-04-01 21:07:39 +00:00
Jim Grosbach
039844acc5 LDRD/STRD instructions should print both Rt and Rt2 in the asm string. 
llvm-svn: 128736
 2011-04-01 20:26:57 +00:00
Johnny Chen
65fe34ae00 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.

llvm-svn: 128734
 2011-04-01 20:21:38 +00:00
Akira Hatanaka
0b476a8e81 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. 
llvm-svn: 128724
 2011-04-01 18:57:38 +00:00
Johnny Chen
17f1f7c322 Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356

llvm-svn: 128722
 2011-04-01 18:26:38 +00:00