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5 Commits

Author SHA1 Message Date
Saleem Abdulrasool
0b2c7d3514 ARM: improve instruction validation for thumb mode 
The ARM Architecture Reference Manual states the following:
  LDM{,IA,DB}:
    The SP cannot be in the list.
    The PC can be in the list.
    If the PC is in the list:
      • the LR must not be in the list
      • the instruction must be either outside any IT block, or the last
        instruction in an IT block.
  POP:
    The PC can be in the list.
    If the PC is in the list:
      • the LR must not be in the list
      • the instruction must be either outside any IT block, or the last
        instruction in an IT block.
  PUSH:
    The SP and PC can be in the list in ARM instructions, but not in Thumb
    instructions.
  STM:{,IA,DB}:
    The SP and PC can be in the list in ARM instructions, but not in Thumb
    instructions.

llvm-svn: 224502
 2014-12-18 05:24:38 +00:00
Rafael Espindola
ffb0b8fbb1 Revert "[Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list for PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090>" 
This reverts commit r223356.

It was failing check-all (MC/ARM/thumb.s in particular).

llvm-svn: 223363
 2014-12-04 14:10:20 +00:00
Jyoti Allur
a4f3d11768 [Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list for PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090> 
llvm-svn: 223356
 2014-12-04 11:52:49 +00:00
Artyom Skrobov
1890ff3a6d [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings) 
llvm-svn: 194263
 2013-11-08 16:25:50 +00:00
Amara Emerson
ece8c5f612 [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly. 
Patch by Artyom Skrobov.

llvm-svn: 191885
 2013-10-03 09:31:51 +00:00