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19115 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
b3eab8c22d Tidy up a bit more, fix tab and remove trailing whitespaces 
llvm-svn: 140186
 2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes
906f64c461 The wrong relocation was being emitted for several SSSE3 instructions. 
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

llvm-svn: 140184
 2011-09-20 21:39:21 +00:00
Bruno Cardoso Lopes
dab989502d Tidy up code! 
llvm-svn: 140183
 2011-09-20 21:39:06 +00:00
Evan Cheng
ead45e2ba6 Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
llvm-svn: 140181
 2011-09-20 21:38:18 +00:00
Akira Hatanaka
4dfc257283 Initial Mips64 support. Patch by Liu with some modifications. 
llvm-svn: 140178
 2011-09-20 20:28:08 +00:00
Andrew Trick
bfac89c238 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
 2011-09-20 18:22:31 +00:00
Craig Topper
df17f1cc99 Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd. 
llvm-svn: 140140
 2011-09-20 07:38:59 +00:00
Andrew Trick
53aeb9f663 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
 2011-09-20 03:17:40 +00:00
Andrew Trick
43ccb48fb2 whitespace 
llvm-svn: 140133
 2011-09-20 03:06:13 +00:00
Jim Grosbach
e936bdc286 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
llvm-svn: 140125
 2011-09-20 00:46:54 +00:00
Jim Grosbach
5ca3bddd26 Thumb2 assembly parsing and encoding for USAX. 
llvm-svn: 140119
 2011-09-20 00:30:45 +00:00
Jim Grosbach
882f1ec6d5 Remove incorrect comments. These are not disassmebly only patterns. 
llvm-svn: 140116
 2011-09-20 00:26:34 +00:00
Jim Grosbach
18a65f1fe6 Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
llvm-svn: 140111
 2011-09-20 00:18:52 +00:00
Jim Grosbach
3de5351645 Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction. 
llvm-svn: 140108
 2011-09-20 00:10:37 +00:00
Jim Grosbach
dd395f87df Thumb CPS definition is not disassembler only. 
llvm-svn: 140106
 2011-09-20 00:00:06 +00:00
Jim Grosbach
794028c0e0 Thumb2 range check on CPS mode immediate. 
llvm-svn: 140105
 2011-09-19 23:58:31 +00:00
Owen Anderson
791a17f64a tMOVSr is not allowed in an IT block either. 
llvm-svn: 140104
 2011-09-19 23:57:20 +00:00
Owen Anderson
3920c43055 CPS instructions are UNPREDICTABLE inside IT blocks. 
llvm-svn: 140102
 2011-09-19 23:47:10 +00:00
Jim Grosbach
011bd172ea Tidy up comments. 
llvm-svn: 140099
 2011-09-19 23:38:34 +00:00
Bruno Cardoso Lopes
de0dc10d6d Fix PR10949. Fix the encoding of VMOVPQIto64rr. 
llvm-svn: 140098
 2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes
7cf7f02c3d Based on the small opt Zvi's patch was trying to achieve, eliminate 
128-bit undef subvector insertion into a 256-bit vector

llvm-svn: 140097
 2011-09-19 23:36:50 +00:00
Jim Grosbach
2341e082fc Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
llvm-svn: 140095
 2011-09-19 23:31:02 +00:00
Jim Grosbach
dd8d66f3aa Thumb2 assembly parsing and encoding for UHASX/UHSAX. 
llvm-svn: 140088
 2011-09-19 23:13:25 +00:00
Jim Grosbach
a5a28c45e5 Thumb2 assembly parsing and encoding for UASX. 
llvm-svn: 140085
 2011-09-19 23:05:22 +00:00
Owen Anderson
25138827ef Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
llvm-svn: 140079
 2011-09-19 22:34:23 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Bruno Cardoso Lopes
9e5ef44daf Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix 
PR10955 and PR10948.

llvm-svn: 140069
 2011-09-19 21:29:24 +00:00
Jim Grosbach
207a337a60 Tidy up a bit. 
llvm-svn: 140050
 2011-09-19 20:31:59 +00:00
Jim Grosbach
c7fa5f0c00 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
llvm-svn: 140047
 2011-09-19 20:29:33 +00:00
Akira Hatanaka
6731be3175 Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't 
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046
 2011-09-19 20:26:02 +00:00
Owen Anderson
4bf9e290e9 Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding. 
llvm-svn: 140041
 2011-09-19 20:00:02 +00:00
Jim Grosbach
57328aa902 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

llvm-svn: 140035
 2011-09-19 18:42:21 +00:00
Owen Anderson
b843f3625d Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
llvm-svn: 140032
 2011-09-19 18:07:10 +00:00
Jim Grosbach
c677995374 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
llvm-svn: 140029
 2011-09-19 17:56:37 +00:00
Nadav Rotem
a6af03c6fb Fix typos in my prev commit, found by Tobi. 
llvm-svn: 140003
 2011-09-18 19:00:23 +00:00
Nadav Rotem
1cfdc59e94 setOperationAction should be done on the return value of the type, not the operands. 
llvm-svn: 140001
 2011-09-18 14:57:03 +00:00
Nadav Rotem
cfc77bc719 When promoting integer vectors we often create ext-loads. This patch adds a 
dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.

llvm-svn: 139995
 2011-09-18 10:39:32 +00:00
Craig Topper
c5a97d12bb Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC. 
llvm-svn: 139993
 2011-09-18 08:03:58 +00:00
Duncan Sands
4149334f09 Synthesize x86 max/min instructions also for vectors (i.e. produce 
maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.

llvm-svn: 139986
 2011-09-17 16:49:39 +00:00
Bruno Cardoso Lopes
f611f6c371 Describe more AVX 128-bit convert instructions without patterns to have 
mayLoad = 1

llvm-svn: 139973
 2011-09-16 23:41:29 +00:00
Owen Anderson
c1f638997d Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
llvm-svn: 139972
 2011-09-16 23:30:01 +00:00
Owen Anderson
aec67a3ea1 Fix bitfield decoding based on Eli's feedback. 
llvm-svn: 139969
 2011-09-16 23:04:48 +00:00
Jim Grosbach
95242bff08 Thumb2 assembly parsing and encoding for SUB(immediate). 
llvm-svn: 139966
 2011-09-16 22:58:42 +00:00
Owen Anderson
5d23e1e5b4 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
llvm-svn: 139965
 2011-09-16 22:42:36 +00:00
Owen Anderson
eae0eee720 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
llvm-svn: 139964
 2011-09-16 22:29:48 +00:00
Owen Anderson
3a487c8c9b Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
llvm-svn: 139958
 2011-09-16 22:17:02 +00:00
Bruno Cardoso Lopes
396b8136bf Add mayLoad attribute to AVX convert instructions, since non of them 
are declared with load patterns. This fix the crash in PR10941. No testcases,
since a fold is triggered and then converted back to the register form
afterwards.

llvm-svn: 139953
 2011-09-16 22:02:14 +00:00
Jim Grosbach
d521731d40 Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

llvm-svn: 139949
 2011-09-16 21:55:56 +00:00
Jim Grosbach
371c88528b Tidy up. 80 columns. 
llvm-svn: 139944
 2011-09-16 21:09:00 +00:00
Owen Anderson
5804085f26 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
llvm-svn: 139943
 2011-09-16 21:08:33 +00:00