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Commit Graph

151274 Commits

Author SHA1 Message Date
Craig Topper
c1b931dafe [InstCombine] Add test cases demonstrating creation of extra bswap instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC
I assume bswap intrinsics are somewhat costly so we should be making sure we are getting rid of them not creating more.

llvm-svn: 307064
2017-07-04 06:50:44 +00:00
Alexander Shaposhnikov
c76d1c1edb [tablegen] Avoid creating a temporary vector in getInstructionCase
Record::getValues returns ArrayRef which has a cast operator
to std::vector, as a result a temporary vector is created
if the type of the variable is const std::vector& 
that is suboptimal in this case.

Differential revision: https://reviews.llvm.org/D34969

Test plan: make check-all

llvm-svn: 307063
2017-07-04 06:16:53 +00:00
Craig Topper
59ed8390ed [X86] Add comment string for broadcast loads from the constant pool.
Summary:
When broadcasting from the constant pool its useful to print out the final vector similar to what we do for normal moves from the constant pool.

I changed only a couple tests that were broadcast focused. One of them had been previously hand tweaked after running the script so that it could check the constant pool declaration. But I think this patch makes that unnecessary now since we can check the comment instead.

Reviewers: spatel, RKSimon, zvi

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34923

llvm-svn: 307062
2017-07-04 05:46:11 +00:00
Alexander Shaposhnikov
1a21ff1278 [llvm] Revert "[tablegen] Avoid creating a temporary vector in getInstructionCase"
Revert rL307059 because of the incorrect commit message & patch, 
will recommit later.

llvm-svn: 307061
2017-07-04 05:37:37 +00:00
Craig Topper
da8c8afca2 [X86] Add RDRAND feature to GLM CPU
Summary: I believe this should be supported on GLM since RDSEED is.

Reviewers: m_zuckerman, zvi, RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34828

llvm-svn: 307060
2017-07-04 05:33:19 +00:00
Alexander Shaposhnikov
8ae1bcfa19 [tablegen] Avoid creating a temporary vector in getInstructionCase
Record::getValues returns ArrayRef which has a cast operator
to std::vector, as a result a temporary vector is created
if the type of the variable is const std::vector& 
that was suboptimal in this case.

Differential revision: https://reviews.llvm.org/D34969

Test plan: make check-all

llvm-svn: 307059
2017-07-04 05:11:30 +00:00
Lang Hames
5ffd7d4185 [Orc] Remove the memory manager argument to addModule, and de-templatize the
symbol resolver argument.

De-templatizing the symbol resolver is part of the ongoing simplification of
ORC layer API.

Removing the memory management argument (and delegating construction of memory
managers for RTDyldObjectLinkingLayer to a functor passed in to the constructor)
allows us to build JITs whose base object layers need not be compatible with
RTDyldObjectLinkingLayer's memory mangement scheme. For example, a 'remote
object layer' that sends fully relocatable objects directly to the remote does
not need a memory management scheme at all (that will be handled by the remote).

llvm-svn: 307058
2017-07-04 04:42:30 +00:00
Dylan McKay
71adee46e4 [AVR] Fix bug which caused assertion errors for some FRMIDX instructions
Previously, if a basic block ended with a FRMIDX instruction, we would
end up doing something like this.

*std::next(MBB.end())

Which would hit an error:

"Assertion `!NodePtr->isKnownSentinel()' failed."

llvm-svn: 307057
2017-07-04 04:40:06 +00:00
Dylan McKay
e74f1e970e [AVR] Add a missing clobber declaration to LPMW
llvm-svn: 307056
2017-07-04 02:52:43 +00:00
Nirav Dave
d98172f6a7 [DAG] Fixed predicate for determining when two frame indices
addresses are comparable. NFCI.

llvm-svn: 307055
2017-07-04 02:20:17 +00:00
NAKAMURA Takumi
e6c7524092 Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"
It broke a testcase.

  Failing Tests (1):
      LLVM :: CodeGen/AMDGPU/alignbit-pat.ll

llvm-svn: 307054
2017-07-04 02:14:18 +00:00
Anton Yartsev
0649b527ea [legalize-types] Clean up softening machinery.
The patch makes SoftenFloatResult/Operand logic just the same as all other legalization routines have: SoftenFloatResult() now fills the SoftenFloats map and SoftenFloatOperand() perform all needed replacements. This prevents softening mashinery from leaving stale entries in SoftenFloats map (that resulted in errors during the legalize type checking) and clarifies softening. The patch replaces https://reviews.llvm.org/D29265.

Differential Revision: https://reviews.llvm.org/D31946

llvm-svn: 307053
2017-07-04 01:08:55 +00:00
Simon Pilgrim
b4da2dc3af [X86][SSE4A] Add support for combining from EXTRQI/INSERTQI shuffles
llvm-svn: 307048
2017-07-03 20:58:16 +00:00
Zvi Rackover
3f342ef7af MathExtras UnitTest: Assert that isPowerOf2(0) is false. NFC.
Summary:
This is a follow-up on D34077. Elena observed that the
correctness of the code relies on isPowerOf2(0) returning false.
Adding a test to cover this corner-case.

Reviewers: delena, davide, craig.topper

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34939

llvm-svn: 307046
2017-07-03 18:42:47 +00:00
Simon Pilgrim
a1dd87c298 [X86][SSE4A] Add SSE4A shuffle tests on pre-SSSE3 hardware
llvm-svn: 307042
2017-07-03 16:53:11 +00:00
Simon Pilgrim
66be995978 [X86][SSE4A] Test SSE4A shuffle combining on SSE42 capable target as well
llvm-svn: 307038
2017-07-03 15:55:54 +00:00
Zvi Rackover
e1f310fac6 DAGCombine: Combine BUILD_VECTOR to TRUNCATE
Summary:
Add a combine for creating a truncate to replace a build_vector composed of extracts with
indices that form a stride-2^N series.

Example:
v8i32 V = ...

v4i32 build_vector((extract_elt V, 0), (extract_elt V, 2), (extract_elt V, 4), (extract_elt V, 6))
-->
v4i32 truncate (bitcast V to v4i64)

Related discussion in llvm-dev about canonicalizing shuffles to
truncates in LLVM IR:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/108936.html.

Reviewers: spatel, RKSimon, efriedma, igorb, craig.topper, wolfgangp, delena

Reviewed By: delena

Subscribers: guyblank, delena, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34077

llvm-svn: 307036
2017-07-03 15:47:40 +00:00
Florian Hahn
80a9b3cbaf [LoopInterchange] Add more debug messages to currentLimitations().
Summary: This makes it easier to find out which limitation prevented this pass from doing its work.

Reviewers: karthikthecool, mzolotukhin, efriedma, mcrosier

Reviewed By: mcrosier

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D34940

llvm-svn: 307035
2017-07-03 15:32:00 +00:00
Sanjay Patel
80ed8f6b2c [x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks.
There were also over-specifications in the RUN params such as CPU model.

llvm-svn: 307033
2017-07-03 15:27:19 +00:00
Ilya Biryukov
11857e40e8 Fixed argument parsing in docker scripts.
llvm-svn: 307031
2017-07-03 15:16:27 +00:00
Sanjay Patel
a2a3a552dd [x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks.
There were also several over-specifications in the RUN params such as CPU model or OS requirement

llvm-svn: 307028
2017-07-03 15:04:05 +00:00
Simon Pilgrim
f76cda29cb [X86][SSE4A] Add tests showing missed opportunities to combine EXTRQI/INSERTQI shuffles
llvm-svn: 307027
2017-07-03 15:01:07 +00:00
Alexander Timofeev
ef2bf78d2f [AMDGPU] Switch scalarize global loads ON by default
Differential revision: https://reviews.llvm.org/D34407

llvm-svn: 307026
2017-07-03 14:54:11 +00:00
Sanjay Patel
9ecbd887bf [x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks.

llvm-svn: 307024
2017-07-03 14:29:45 +00:00
Sanjay Patel
fca921ea9a [InstCombine] move and improve tests for cmp-intrinsic; NFC
llvm-svn: 307022
2017-07-03 14:07:40 +00:00
Benjamin Kramer
3a7e958ff3 Revert "[GVN] Recommit the patch "Add phi-translate support in scalarpre"."
This reverts commit r306313. This breaks selfhost at -O3 and PR33652.
Let me know if you need additional information on reproducing the issue.

llvm-svn: 307021
2017-07-03 12:23:10 +00:00
Igor Breger
c7a849195d [GlobalISel][X86] fix %ptr(p0) = G_CONSTANT selection.
llvm-svn: 307019
2017-07-03 11:06:54 +00:00
Hiroshi Inoue
8d919daa58 fix trivial typos in comments; NFC
llvm-svn: 307004
2017-07-03 06:32:59 +00:00
Craig Topper
01ff7011f7 [InstCombine] Add a TODO for a probable missing single use check. NFC
Will try to fix it soon, but in case I forget.

llvm-svn: 307003
2017-07-03 05:54:16 +00:00
Craig Topper
c37262b51c [InstCombine] Support BITWISE_OP( BSWAP(x), CONSTANT ) -> BSWAP( BITWISE_OP(x, BSWAP(CONSTANT) ) ) for splat vectors.
llvm-svn: 307002
2017-07-03 05:54:15 +00:00
Craig Topper
3084c00867 [InstCombine] Add test cases for BITWISE_OP( BSWAP(x), CONSTANT ) -> BSWAP( BITWISE_OP(x, BSWAP(CONSTANT) ) ) with splat vectors. NFC
llvm-svn: 307001
2017-07-03 05:54:14 +00:00
Craig Topper
8e27138544 [InstCombine] Remove support for BITWISE_OP(CONSTANT, BSWAP(x)) -> BSWAP(OP(BSWAP(CONSTANT), x)).
Constants were already canonicalized to the right hand side before we got here.

llvm-svn: 307000
2017-07-03 05:54:13 +00:00
Craig Topper
9a177eb374 [InstCombine] Support BITWISE_OP(BSWAP(A),BSWAP(B))->BSWAP(BITWISE_OP(A, B)) for vectors.
llvm-svn: 306999
2017-07-03 05:54:13 +00:00
Craig Topper
e639633abd [InstCombine] Add test cases showing missed opportunity to fold BITWISE_OP(BSWAP(A),BSWAP(B))->BSWAP(BITWISE_OP(A, B)) for vectors. NFC
llvm-svn: 306998
2017-07-03 05:54:12 +00:00
Craig Topper
6ccf4facf7 [InstCombine] Remove an if that should have been guaranteed by the caller. Replace with an assert. NFC
llvm-svn: 306997
2017-07-03 05:54:11 +00:00
Matt Arsenault
8101679254 AMDGPU: Add operand target flags serialization
llvm-svn: 306995
2017-07-02 23:21:48 +00:00
Simon Pilgrim
04c1c32db4 [X86][AVX512] Test AVX512VPOPCNTDQ CTPOP with/without AVX512BW
llvm-svn: 306991
2017-07-02 19:52:20 +00:00
Simon Pilgrim
b4221e1609 [X86][AVX512VPOPCNTDQ] Improve support for v16i8/v8i16/v16i16/ CTPOP
Zero extend to v16i32/v8i64, use VPOPCNTDQ instructions and truncate back.

llvm-svn: 306990
2017-07-02 19:32:37 +00:00
Simon Pilgrim
ad99280433 [X86][AVX512] Cleanup tzcnt tests triples and attributes
Avoid use of specific -mcpu

llvm-svn: 306989
2017-07-02 18:51:48 +00:00
Simon Pilgrim
a96d6332c0 [X86][AVX512] Cleanup popcnt tests triples and attributes
Avoid use of specific -mcpu

llvm-svn: 306988
2017-07-02 18:35:22 +00:00
Craig Topper
79e61ab186 [IR] Remove unnecessary operator new from ConstantDataArray and ConstantDataVector. They inherit an identical version from ConstantData. NFC
llvm-svn: 306987
2017-07-02 17:08:44 +00:00
Simon Pilgrim
056330f200 [InstCombine] Use m_BitReverse pattern match helper. NFCI.
llvm-svn: 306986
2017-07-02 16:31:16 +00:00
Sanjay Patel
869dea5853 [InstCombine] fix crash when folding cmp+bswap vector
We assumed the constant was a scalar when creating the replacement operand.

Also, improve tests for this fold and move the tests for this fold to their own file.
I'll move the related and missing tests to this file as a follow-up.  

llvm-svn: 306985
2017-07-02 16:05:11 +00:00
Sanjay Patel
8ee028c8d9 [x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks.

llvm-svn: 306984
2017-07-02 15:24:08 +00:00
Sanjay Patel
f06e47122e [x86] remove unnecessary RUN for test after auto-generating checks; NFC
llvm-svn: 306983
2017-07-02 15:16:17 +00:00
Sanjay Patel
f4bcdab032 [x86] update test to use FileCheck and auto-generate checks; NFC
llvm-svn: 306982
2017-07-02 15:15:18 +00:00
Sanjay Patel
5dc61a737c [x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks.

llvm-svn: 306981
2017-07-02 14:50:35 +00:00
Sanjay Patel
cf226a8e8f [InstCombine] look through bswap/bitreverse for equality comparisons
I noticed this missed bswap optimization in the CGP memcmp() expansion, 
and then I saw that we don't have the fold in InstCombine.

Differential Revision: https://reviews.llvm.org/D34763

llvm-svn: 306980
2017-07-02 14:34:50 +00:00
NAKAMURA Takumi
89049af28b llvm/test/Transforms/LoopVectorize/X86/slm-no-vectorize.ll: -debug is available in +Asserts.
llvm-svn: 306979
2017-07-02 14:25:27 +00:00
Simon Pilgrim
ce6261d7a2 [X86][SSE] Attempt to combine 64-bit and 32-bit shuffles to unary shuffles before bit shifts
We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive

llvm-svn: 306978
2017-07-02 14:16:25 +00:00