RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 11:33:24 +02:00
Code Issues Projects Releases Wiki Activity
132,642 Commits 4 Branches 5 Tags 704 MiB
5407a70fdf
Commit Graph

237 Commits

Author SHA1 Message Date
Craig Topper
5407a70fdf [AVX512] Remove gcc builtin name from masked load intrinsics so they can be custom handled by clang to create generic masked load intrinsics instead of using the x86 specific ones. 
The intrinsics will be removed in a future commit.

llvm-svn: 271252
 2016-05-31 06:42:51 +00:00
Craig Topper
cb79936a4b [AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead. 
The intrinsics will be autoupgraded to the same generic masked stores.

llvm-svn: 271245
 2016-05-31 01:50:02 +00:00
Craig Topper
4f195e8edb [X86] Remove SSE/AVX unaligned store intrinsics as clang no longer uses them. Auto upgrade to native unaligned store instructions. 
llvm-svn: 271236
 2016-05-30 23:15:56 +00:00
Simon Pilgrim
6ec0f7efbc [X86][SSE] (Reapplied) Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) 
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.

Reapplied now that the the companion patch (D20684) removes/auto-upgrade the clang intrinsics has been committed.

Differential Revision: http://reviews.llvm.org/D20686

llvm-svn: 271131
 2016-05-28 18:03:41 +00:00
Simon Pilgrim
99e3cf65ff Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) 
llvm-svn: 270976
 2016-05-27 09:02:25 +00:00
Simon Pilgrim
c8925e270b [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) 
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.

A companion patch (D20684) removes/auto-upgrade the clang intrinsics.

Differential Revision: http://reviews.llvm.org/D20686

llvm-svn: 270973
 2016-05-27 08:49:15 +00:00
Simon Pilgrim
1a1ddc32da [X86][SSE] Replace (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) lossless conversion intrinsics with generic IR 
Followup to D20528 clang patch, this removes the (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) llvm intrinsics and auto-upgrades to sitofp/fpext instead.

Differential Revision: http://reviews.llvm.org/D20568

llvm-svn: 270678
 2016-05-25 08:59:18 +00:00
Craig Topper
4710ab1424 [X86] Remove the llvm.x86.sse2.storel.dq intrinsic. It hasn't been used in a long time. 
llvm-svn: 270677
 2016-05-25 06:56:32 +00:00
Simon Pilgrim
288380872a [X86][SSE] The int_x86_sse41_pmovsx* intrinsics are no longer in use (not since D13002!) 
llvm-svn: 270497
 2016-05-23 22:01:24 +00:00
Asaf Badouh
fd565dbaaa [X86][RTM] _xabort() should not have "noreturn" attribute 
Differential Revision: http://reviews.llvm.org/D20518

llvm-svn: 270437
 2016-05-23 14:04:17 +00:00
Ashutosh Nema
0cfbe42fbc Add new flag and intrinsic support for MWAITX and MONITORX instructions 
Summary:

MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.

The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction execution
and enter an implementation-dependent optimized state until occurrence of a
class of events.

Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.

These instructions are enabled for AMD's bdver4 architecture.

Patch by Ganesh Gopalasubramanian!

Reviewers: echristo, craig.topper, RKSimon
Subscribers: RKSimon, joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D19795

llvm-svn: 269911
 2016-05-18 11:59:12 +00:00
Craig Topper
ff59cd3fa2 [X86] Remove GCC builtin from add/sub/mul/div ss/sd intrinsics. These haven't been used as builtins in clang for a long time. 
Can probably remove the intrinsics entirely, but that will require more work.

llvm-svn: 269876
 2016-05-18 01:36:25 +00:00
Craig Topper
9a772121e9 [AVX512] Fix mask argument type for insertf32x4/inserti32x4. 
llvm-svn: 269616
 2016-05-15 21:24:45 +00:00
Craig Topper
85f7733f7c [AVX512] Change 512-bit insertf32x4/inserti32x4 builtin name to match gcc. 
Clang doesn't currently use this builtin. Will fix that soon.

llvm-svn: 269609
 2016-05-15 20:09:34 +00:00
Craig Topper
d86227613c [AVX512] Make the permd intrinsics take a 32-bit immediate to match the software spec. 
llvm-svn: 269579
 2016-05-14 21:13:20 +00:00
Craig Topper
fe0638b35b [AVX512] Fix types for pshufd intrinsics. The immediate is the second argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file. 
Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs.

llvm-svn: 269526
 2016-05-14 00:47:18 +00:00
Craig Topper
1a7c59b5bb [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result. 
llvm-svn: 268891
 2016-05-09 05:34:12 +00:00
Michael Zuckerman
4cc752e542 Fixing wrong mask size error. From __mmask8 to __mmask16. 
Was reviewed over the shoulder by AsafBadouh.
Connected to review http://reviews.llvm.org/D19195.

llvm-svn: 267379
 2016-04-25 05:27:51 +00:00
NAKAMURA Takumi
a7b5d1c953 Untabify. 
llvm-svn: 267096
 2016-04-22 01:33:50 +00:00
Nicolai Haehnle
0127d62008 Split IntrReadArgMem into IntrReadMem and IntrArgMemOnly 
Summary:
IntrReadWriteArgMem simply becomes IntrArgMemOnly.

So there are fewer intrinsic properties that express their orthogonality
better, and correspond more closely to the corresponding IR attributes.

Suggested by: Philip Reames

Reviewers: joker.eph, reames, tstellarAMD

Subscribers: jholewinski, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19291

llvm-svn: 267021
 2016-04-21 17:48:02 +00:00
Simon Pilgrim
5ae313a9f9 Removed trailing whitespace 
llvm-svn: 263871
 2016-03-19 02:05:33 +00:00
Michael Zuckerman
daef31c3f8 [LLVM][AVX512] PSRLWI Chnage imm8 to int 
Differential Revision: http://reviews.llvm.org/D17753

llvm-svn: 262592
 2016-03-03 08:54:05 +00:00
Michael Zuckerman
823b8e16d6 [LLVM][AVX512]PSRAWI Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17705

llvm-svn: 262480
 2016-03-02 12:05:07 +00:00
Michael Zuckerman
71f617e26e [LLVM][AVX512] PSRL{DI|QI} Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17713

llvm-svn: 262353
 2016-03-01 17:46:32 +00:00
Michael Zuckerman
c05422513f [AVX512][PSRAQ][PSRAD] Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17692

llvm-svn: 262320
 2016-03-01 11:36:23 +00:00
Michael Zuckerman
c4dc2f4ba2 [AVX512][PSLLW ][PSLLV] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17684

llvm-svn: 262176
 2016-02-28 07:32:10 +00:00
Michael Zuckerman
d1c409a5af [LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17538

llvm-svn: 261725
 2016-02-24 08:39:05 +00:00
Michael Zuckerman
285264f877 [AVX512][PRORQ][PRORD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17024

llvm-svn: 261198
 2016-02-18 09:52:12 +00:00
Michael Zuckerman
c705af63bb [AVX512][PROLQ][PROLD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D16983

llvm-svn: 260101
 2016-02-08 15:13:32 +00:00
Igor Breger
4e8ad22be9 AVX512: Change builtin function name for scalar intrinsics. Add "mask" to function name to reflect the function behavior. 
Differential Revision: http://reviews.llvm.org/D16958

llvm-svn: 260089
 2016-02-08 12:38:03 +00:00
Asaf Badouh
5bbbfafa66 [X86][AVX512] add intrinsics of Scalar FP to integer conversion with rounding mode 
Differential Revision: http://reviews.llvm.org/D16629

llvm-svn: 260033
 2016-02-07 14:59:13 +00:00
Igor Breger
60ac21f165 AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation. 
Differential Revision: http://reviews.llvm.org/D16813

llvm-svn: 260024
 2016-02-07 08:30:50 +00:00
Michael Zuckerman
d8de4a9888 [AVX512] add vfmadd132ss and vfmadd132sd Intrinsic 
Differential Revision: http://reviews.llvm.org/D16589

llvm-svn: 259789
 2016-02-04 14:41:08 +00:00
Asaf Badouh
7d5bdf84bb [X86][AVX512VBMI] add encoding and intrinsics for Multishift 
Differential Revision: http://reviews.llvm.org/D16399

llvm-svn: 259363
 2016-02-01 15:48:21 +00:00
Asaf Badouh
547a7d4edb [X86][AVX512] small fix in ptestm intrinsics 
move ptestm{q|d} intrinsics from patterns form (in td file) to the intrinsics table

Differential Revision: http://reviews.llvm.org/D16633

llvm-svn: 259029
 2016-01-28 08:33:22 +00:00
Michael Zuckerman
847379aa25 [AVX512] Adding PTESTNMB/D/W/Q instruction 
Differential Revision: http://reviews.llvm.org/D16520

llvm-svn: 258688
 2016-01-25 14:43:23 +00:00
Michael Zuckerman
5131ab0907 [AVX512] Adding PTESTMB/W/D/Q instruction 
Differential Revision: http://reviews.llvm.org/D16519

llvm-svn: 258686
 2016-01-25 13:27:32 +00:00
Asaf Badouh
ec3729528a [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned 52bit integer 
VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
 VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators

Differential Revision: http://reviews.llvm.org/D16407

llvm-svn: 258680
 2016-01-25 11:14:24 +00:00
Igor Breger
f91b2666bb AVX512: VMOVDQU8/16/32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16137

llvm-svn: 258657
 2016-01-24 08:04:33 +00:00
Igor Breger
73167c5d63 AVX512: Masked move intrinsic implementation. 
Implemented intrinsic for the follow instructions (reg move) : VMOVDQU8/16, VMOVDQA32/64, VMOVAPS/PD.

Differential Revision: http://reviews.llvm.org/D16316

llvm-svn: 258398
 2016-01-21 14:18:11 +00:00
Michael Zuckerman
42638cd6f9 [AVX512] Adding VPERMT2B and VPERMI2B Intrinsics 
Differential Revision: http://reviews.llvm.org/D16398

llvm-svn: 258397
 2016-01-21 13:36:01 +00:00
Michael Zuckerman
852ec66515 [AVX512] Adding VPERMB Intrinsics 
Differential Revision: http://reviews.llvm.org/D16296

llvm-svn: 258316
 2016-01-20 15:24:56 +00:00
Igor Breger
866bd3ac74 AVX512: Store (MOVNTPD, MOVNTPS, MOVNTDQ) using non-temporal hint intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16350

llvm-svn: 258309
 2016-01-20 13:11:47 +00:00
Asaf Badouh
19e99238a0 [X86][AVX512]fix dag & add intrinsics for fixupimm 
cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics

Differential Revision: http://reviews.llvm.org/D16313

llvm-svn: 258124
 2016-01-19 14:21:39 +00:00
Igor Breger
7327a3bf3b AVX512: Masked store intrinsic implementation. 
Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.

Differential Revision: http://reviews.llvm.org/D16271

llvm-svn: 258047
 2016-01-18 13:52:57 +00:00
Michael Zuckerman
04a3249a24 [AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics 
Differential Revision: http://reviews.llvm.org/D16189

llvm-svn: 258008
 2016-01-17 11:33:29 +00:00
Michael Zuckerman
365c9dfcf3 [AVX512] Adding VPERMQ VPERMPD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16194

llvm-svn: 258006
 2016-01-17 08:32:14 +00:00
Igor Breger
bd173e545a AVX512: VMOVDQA32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16142

llvm-svn: 257749
 2016-01-14 07:56:04 +00:00
Michael Zuckerman
dfb762ecb8 [AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics . 
Differential Revision: http://reviews.llvm.org/D16111 

llvm-svn: 257604
 2016-01-13 14:59:19 +00:00
Michael Zuckerman
7d1a571f3e [AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics 
Differential Revision:http://reviews.llvm.org/D16071

llvm-svn: 257601
 2016-01-13 14:25:21 +00:00